ST92F124 datasheet(210/429 Pages) STMICROELECTRONICS

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MULTIFUNCTION TIMER (MFT)

MULTIFUNCTION TIMER (Cont’d)

DMA ADDRESS POINTER REGISTER (DAPR)

R241 - Read/Write

Reset value: undefined

Bits 7:2 = DAP[7:2]: MSB of DMA address regis-

ter location.

These are the most significant bits of the DMA ad-

dress register location programmable by software.

The DAP2 bit may also be toggled by hardware if

the Timer DMA section for the Compare 0 channel

is configured in Swap mode.

Note: During a DMA transfer with the Register

File, the DAPR is not used; however, in Swap

mode, DAP2 is used to point to the correct table.

Bit 1 = DMA-SRCE: DMA source selection.

This bit is fixed by hardware.

0: DMA source is a Capture on REG0R register

1: DMA destination is a Compare on the CMP0R

Bit 0 = PRG/DAT: DMA memory selection.

This bit is set and cleared by software. It is only

meaningful if DCPR.REG/MEM=0.

0: The ISR register is used to extend the address

of data transferred by DMA (see MMU chapter).

1: The DMASR register is used to extend the ad-

dress of data transferred by DMA (see MMU

chapter).

INTERRUPT VECTOR REGISTER (T_IVR)

R242 - Read/Write

Reset value: xxxx xxx0

This register is used as a vector, pointing to the

16-bit interrupt vectors in memory which contain

the starting addresses of the three interrupt sub-

routines managed by each timer.

Only one Interrupt Vector Register is available for

each timer, and it is able to manage three interrupt

groups, because the 3 least significant bits are

fixed by hardware depending on the group which

generated the interrupt request.

In order to determine which request generated the

interrupt within a group, the T_FLAGR register can

be used to check the relevant interrupt source.

Bits 7:3 = V[4:0]: MSB of the vector address.

These bits are user programmable and contain the

five most significant bits of the Timer interrupt vec-

tor addresses in memory. In any case, an 8-bit ad-

dress can be used to indicate the Timer interrupt

vector locations, because they are within the first

256 memory locations (see Interrupt and DMA

chapters).

Bits 2:1 = W[1:0]: Vector address bits.

These bits are equivalent to bit 1 and bit 2 of the

Timer interrupt vector addresses in memory. They

are fixed by hardware, depending on the group of

sources which generated the interrupt request as

follows:.

Bit 0 = This bit is forced by hardware to 0.

DAP7 DAP6 DAP5 DAP4 DAP3 DAP2

DMA

SRCE

PRG

/DAT

REG/MEM PRG/DAT

DMA Source/Destination

ISR register used to address

memory

DMASR register used to address

memory

Interrupt Source

Overflow/Underflow even interrupt

Not available

Capture event interrupt

Compare event interrupt

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