ST92F124 datasheet(244/429 Pages) STMICROELECTRONICS

部件名	ST92F124

功能描述	8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E3 TM(EMULATED EEPROM), CAN 2.0B AND J1850 BLPD

PDF	429 Pages

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制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

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ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (SCI-A)

ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.6.4.7 Parity definition

Even parity: The parity bit is calculated to obtain

an even number of “1s” inside the frame made of

the 7 or 8 LSB bits (depending on whether M is

equal to 0 or 1) and the parity bit.

Ex: data=00110101; 4 bits set => parity bit will be

0 if even parity is selected (PS bit = 0).

Odd parity: The parity bit is calculated to obtain

an odd number of “1s” inside the frame made of

the 7 or 8 LSB bits (depending on whether M is

equal to 0 or 1) and the parity bit.

Ex: data=00110101; 4 bits set => parity bit will be

1 if odd parity is selected (PS bit = 1).

Transmission mode: If the PCE bit is set then the

MSB bit of the data written in the data register is

not transmitted but is changed by the parity bit.

Reception mode: If the PCE bit is set then the in-

terface checks if the received data byte has an

even number of “1s” if even parity is selected

(PS=0) or an odd number of “1s” if odd parity is se-

lected (PS=1). If the parity check fails, the PE flag

is set in the SCISR register and an interrupt is gen-

erated if PCIE is set in the SCICR1 register.

ST92F124 数据表(PDF) 244 Page - STMicroelectronics