ST92F124 datasheet(247/429 Pages) STMICROELECTRONICS

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ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (SCI-A)

ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (Cont’d)

CONTROL REGISTER 2 (SCICR2)

R244 - Read/Write

Reset Value: 0000 0000 (00h)

Bit 7 = TIE Transmitter interrupt enable.

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SCI interrupt is generated whenever

TDRE=1 in the SCISR register

Bit 6 = TCIE Transmission complete interrupt ena-

ble

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SCI interrupt is generated whenever TC=1 in

the SCISR register

Bit 5 = RIE Receiver interrupt enable.

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SCI interrupt is generated whenever OR=1

or RDRF=1 in the SCISR register

Bit 4 = ILIE Idle line interrupt enable.

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SCI interrupt is generated whenever IDLE=1

in the SCISR register.

Bit 3 = TE Transmitter enable.

This bit enables the transmitter. It is set and

cleared by software.

0: Transmitter is disabled, the TDO pin is in high

impedance

1: Transmitter is enabled

Note: during transmission, a “0” pulse on the TE

bit (“0” followed by “1”) sends a preamble after the

current word.

Bit 2 = RE Receiver enable.

This bit enables the receiver. It is set and cleared

by software.

0: Receiver is disabled, it resets the RDRF, IDLE,

OR, NF and FE bits of the SCISR register

1: Receiver is enabled and begins searching for a

start bit

Bit 1 = RWU Receiver wake-up.

This bit determines if the SCI is in mute mode or

not. It is set and cleared by software and can be

cleared by hardware when a wake-up sequence is

recognized.

0: Receiver in active mode

1: Receiver in mute mode

Bit 0 = SBK Send break.

This bit set is used to send break characters. It is

set and cleared by software.

0: No break character is transmitted

1: Break characters are transmitted

Notes:

– If the SBK bit is set to “1” and then to “0”, the

transmitter will send a BREAK word at the end of

the current word.

– The ITEI0 bit in the SITRH register (See Inter-

rupts Chapter) must be set to enable the SCI-A

interrupt as the SCI-A interrupt is a rising edge

event.

CONTROL REGISTER 3 (SCICR3)

R255 - Read/Write

Reset Value: 0000 0000 (00h)

Bit 7 = Reserved

Bit 6 = LINE LIN mode Enable.

This bit is set and cleared by software.

0: LIN master mode disabled

1: LIN master mode enabled

LIN master mode enables the capability to send

LIN Synch Breaks (13 low bits) using the SBK bit

in the SCICR2 register. In transmission, the LIN

Synch Break low phase duration is shown as be-

low:

Bits 5:0 = Reserved

TIE

TCIE

RIE

ILIE

RWU

SBK

LINE

Number of low bits sent

during a LIN Synch Break

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