ST92F124 datasheet(282/429 Pages) STMICROELECTRONICS

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I2C BUS INTERFACE

I2C BUS INTERFACE (Cont’d)

INTERRUPT MASK REGISTER (I2CIMR)

R255 - Read / Write

Reset Value: 00xx 0000 (x0h)

Bit 7 = RXDM Receiver DMA Mask.

0: DMA reception disable.

1: DMA reception enable

RXDM is reset by hardware when the transaction

counter value decrements to zero, that is when a

Receiver End Of Block interrupt is issued.

Bit 6 = TXDM Transmitter DMA Mask.

0: DMA transmission disable.

1: DMA transmission enable.

TXDM is reset by hardware when the transaction

counter value decrements to zero, that is when a

Transmitter End Of Block interrupt is issued.

Bit 5 = REOBP Receiver DMA End Of Block Flag.

REOBP should be reset by software in order to

avoid undesired interrupt routines, especially in in-

itialization routine (after reset) and after entering

the End Of Block interrupt routine.Writing “0” in

this bit will cancel the interrupt request

Note: REOBP can only be written to “0”.

0: End of block not reached.

1: End of data block in DMA receiver detected

Bit 4 = TEOBP Transmitter DMA End Of Block TE-

OBP should be reset by software in order to avoid

undesired interrupt routines, especially in initializa-

tion routine (after reset) and after entering the End

Of Block interrupt routine.Writing “0” will cancel the

interrupt request.

Note: TEOBP can only be written to “0”.

0: End of block not reached

1: End of data block in DMA transmitter detected.

Bit 3 = Reserved. This bit must be cleared.

Bit 2 = IERRM Error Condition interrupt mask bit.

This bit enables/ disables the Error interrupt.

0: Error interrupt disabled.

1: Error Interrupt enabled.

Bit 1 = IRXM Data Received interrupt mask bit.

This bit enables/ disables the Data Received and

Receive DMA End of Block interrupts.

0: Interrupts disabled

1: Interrupts enabled

Note: This bit has no effect on DMA transfer

Bit 0 = ITXM Peripheral Ready To Transmit inter-

rupt mask bit.

This bit enables/ disables the Peripheral Ready To

Transmit and Transmit DMA End of Block inter-

rupts.

0: Interrupts disabled

1: Interrupts enabled

Note: This bit has no effect on DMA transfer.

RXDM TXDM REOBP TEOBP

IERRM IRXM ITXM

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