ST92F124 datasheet(286/429 Pages) STMICROELECTRONICS

286 / 429 page

286/429

J1850 Byte Level Protocol Decoder (JBLPD)

J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)

10.9.3 Functional Description

10.9.3.1 J1850 protocol symbols

J1850 symbols are defined as a duration (in micro-

seconds or clock cycles) and a state which can be

either an active state (logic high level on VPWO)

or a passive state (logic low level on VPWO).

An idle J1850 bus is in a passive state.

Any symbol begins by changing the state of the

VPW line. The line is in this state for a specific du-

ration depending on the symbol being transmitted.

Durations, and hence symbols, are measured as

time between successive state transitions. Each

symbol has only one level transition of a specific

duration.

Symbols for logic zero and one data bits can be ei-

ther a high or a low level, but all other symbols are

defined at only one level.

Each symbol is placed directly next to another.

Therefore, every level transition means that anoth-

er symbol has begun.

Data bits of a logic zero are either a short duration

if in a passive state or a long duration if in an active

state. Data bits of a logic one are either a long du-

ration if in a passive state or a short duration if in

an active state. This ensures that data logic zeros

predominate during bus arbitration.

An eight bit data byte transmission will always

have eight transitions. For all data byte and CRC

byte transfers, the first bit is a passive state and

the last bit is an active state.

For the duration of the VPW, symbols are ex-

pressed in terms of Tv’s (or VPW mode timing val-

ues). J1850 symbols and Tv values are described

in the SAE J1850 specification, in Table 52 and in

Table 53.

An ignored Tv I.D. occurs for level transitions

which occur in less than the minimum time re-

quired for an invalid bit detect. The VPW encoder

does not recognize these characters as they are

filtered out by the digital filter. The VPW decoder

does not resynchronize its counter with either

edge of “ignored” pulses. Therefore, the counter

which times symbols continues to time from the

last transition which occurred after a valid symbol

(including the invalid bit symbol) was recognized.

A symbol recognized as an invalid bit will resyn-

chronize the VPW decoder to the invalid bit edges.

In the case of the reception of an invalid bit, the

JBLPD peripheral will set the IBD bit in the ER-

ROR register. The JBLPD peripheral shall termi-

nate any transmissions in progress, and disable

receive transfers and RDRF flags until the VPW

decoder recognizes a valid EOF symbol from the

bus.

The JBLPD’s state machine handles all the Tv

l.D.s in accordance with the SAE J1850 specifica-

tion.

Note: Depending on the value of a control bit, the

polarity of the VPWI input can be the same as the

J1850 bus or inverted with respect to it.

Table 52. J1850 Symbol definitions

Table 53. J1850 VPW Mode Timing Value (Tv)

definitions (in clock cycles)

Symbol

Definition

Data Bit Zero

Passive for Tv1 or Ac-

tive for Tv2

Data Bit One

Passive for Tv2 or Ac-

tive for Tv1

Start of Frame (SOF)

Active for Tv3

End of Data (EOD)

Passive for Tv3

End of Frame (EOF)

Passive for Tv4

Inter Frame Separation (IFS)

Passive for Tv6

IDLE Bus Condition (IDLE)

Passive for > Tv6

Normalization Bit (NB)

Active for Tv1 or Tv2

Break (BRK)

Active for Tv5

Pulse Width

or Tv I.D.

Minimum

Duration

Nominal

Duration

Maximum

Duration

Ignored

N/A

<=7

Invalid Bit

N/A

<=34

Tv1

>34

<=96

Tv2

>96

128

<=163

Tv3

>163

200

<=239

Tv4

>239

280

N/A

Tv5

>239

300

N/A

Tv6

>280

300

N/A

ST92F124 数据表(PDF) 286 Page - STMicroelectronics

ST92F124 数据表(HTML) 286 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

ST92F124 数据表(PDF) 286 Page - STMicroelectronics

ST92F124 数据表(HTML) 286 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载