ST92F124 datasheet(288/429 Pages) STMICROELECTRONICS

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J1850 Byte Level Protocol Decoder (JBLPD)

J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)

If the J1850 bus was IDLE at the time the first data

byte and opcode are written, the transmitter will

immediately transfer data from the TXDATA regis-

ter to the transmit shift register. The TRDY bit will

once again be set signifying the readiness to ac-

cept a new data byte. The second data byte can

then be written followed by the respective opcode.

In the case of the last data byte, the TXOP register

should be written with the MSG+CRC opcode. The

transmitter will transmit the internally generated

CRC after the last bit of the data byte. Once the

TRDY bit is set signifying the acceptance of the

last data byte, the first byte of the next message

can be queued by writing the TXDATA register fol-

lowed by a TXOP register write. The block will wait

until the current data and the CRC data byte are

sent out and a new IFS has expired before trans-

mitting the new data. This is the case even if IFR

data reception takes place in the interim.

Lost arbitration any time during the transfer of type

0 data will be honoured by immediately relinquish-

ing control to the higher priority message. The TLA

bit in the STATUS register is set accordingly and

an interrupt will be generated assuming the

TLA_M bit in the IMR register is set. It is responsi-

bility of the user program to re-send the message

beginning with the first byte if desired. This may be

done at any time by rewriting only the TXOP regis-

ter if the TXDATA contents have not changed.

Any transmitted data and CRC bytes during the

transmit frame will also be received and trans-

ferred to the RXDATA register if the corresponding

message filter bit is set in the FREG[0:31] regis-

ters. If the corresponding bit is not set in

FREG[0:31], then the transmitted data is also not

transferred to RXDATA. Also, the RDRF will not

get set during frame and receive events such as

RDOF & EODM.

NOTE: The correct procedure for transmitting is to

write first the TXDATA register and then the TXOP

10.9.6.4 DMA

Management in

Transmission

Mode).

Transmitting a Type 1 IFR

The user program will decide to transmit an IFR

type 1 byte in response to a message which is cur-

rently being received (See Figure 132). It does so

by writing the IFR1 opcode to the TXOP register.

Transmitting IFR data type 1 requires only a single

write of the TXOP register with the IFR1 opcode

set. The MLC[3:0] bits should be set to the proper

“byte-received-count-required-before-IFR’ing” val-

ue. If no error conditions (IBD, IFD, TRA, RBRK or

CRCE) exist to prevent transmission, the JBLPD

peripheral will then transmit out the contents of the

PADDR register at the next EOD nominal time pe-

riod or at a time greater than the EOD minimum

time period if a falling edge is detected on filtered

J1850 bus line signifying another transmitter is be-

ginning early. The NB1 symbol precedes the PAD-

DR register value and is followed with an EOF de-

limiter. The TRDY flag is cleared on the write of the

TXOP register. The TRDY bit is set once the NB1

begins transmitting.

Although the JBLPD should never lose arbitration

for data in the IFR portion of a type 1 frame, higher

priority messages are always honoured under the

rules of arbitration. If arbitration is lost then the

VPWO line is set to the passive state. The TLA bit

in the STATUS register is set accordingly and an

interrupt will be generated if enabled. The IFR1 is

not retried. It is lost if the JBLPD peripheral loses

arbitration. Also, the data that made it out on the

bus will be received in the RXDATA register if not

put into sleep mode. Note that for the transmitter to

synchronize to the incoming signals of a frame, an

IFR should be queued before an EODM is re-

ceived for the present frame.

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