ST92F124 datasheet(299/429 Pages) STMICROELECTRONICS

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J1850 Byte Level Protocol Decoder (JBLPD)

J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)

Note: After an MCU reset, the DMA requests of

the JBLPD have a higher priority than the interrupt

requests.

If the DMASUSP bit of the OPTIONS register is

set, while the ERROR and TLA flags are set, no

DMA transfer will be performed, allowing the re-

lavent interrupt routines to manage each condition

and, if necessary, disable the DMA transfer (Refer

to Section 10.9.6 DMA Features).

Table 56. JBLPD internal priority levels

The user can program the most significant bits of

the interrupt vectors by writing the V[7:3] bits of the

IVR register. Starting from the value stored by the

user, the JBLPD sets the three least significant

bits of the IVR register to produce four interrupt

vectors that are associated with interrupt sources

as shown in Table 57.

Table 57. JBLPD interrupt vectors

Each interrupt source has a pending bit in the

STATUS register, except the DMA interrupt sourc-

es that have the interrupt pending bits located in

the PRLR register.

These bits are set by hardware when the corre-

sponding interrupt event occurs. An interrupt re-

quest is performed only if the related mask bits are

set in the IMR register and the JBLPD has priority.

The pending bits have to be reset by the user soft-

ware. Note that until the pending bits are set (while

the corresponding mask bits are set), the JBLPD

processes interrupt requests. So, if at the end of

an interrupt routine the related pending bit is not

reset, another interrupt request is performed.

To reset the pending bits, different actions have to

be done, depending on each bit: see the descrip-

tion of the STATUS and PRLR registers.

Priority Level

Interrupt Source

Higher

ERROR, TLA

EODM, EOFM

RDRF, REOB

Lower

TRDY, TEOB

Interrupt Vector

Interrupt Source

V[7:3] 000b

ERROR, TLA

V[7:3] 010b

EODM, EOFM

V[7:3] 100b

RDRF, REOB

V[7:3] 110b

TRDY, TEOB

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