数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

ST92F124 数据表(PDF) 308 Page - STMicroelectronics

部件名 ST92F124
功能描述  8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E3 TM(EMULATED EEPROM), CAN 2.0B AND J1850 BLPD
PDF  429 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST92F124 数据表(HTML) 308 Page - STMicroelectronics

Back Button ST92F124 Datasheet HTML 304Page - STMicroelectronics ST92F124 Datasheet HTML 305Page - STMicroelectronics ST92F124 Datasheet HTML 306Page - STMicroelectronics ST92F124 Datasheet HTML 307Page - STMicroelectronics ST92F124 Datasheet HTML 308Page - STMicroelectronics ST92F124 Datasheet HTML 309Page - STMicroelectronics ST92F124 Datasheet HTML 310Page - STMicroelectronics ST92F124 Datasheet HTML 311Page - STMicroelectronics ST92F124 Datasheet HTML 312Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 308 / 429 page
background image
308/429
J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Bit 7:4 = MLC[3:0] Message Length Count.
Message Length Count bits 3 to 0 are written when
the program writes one of the IFR opcodes. Upon
detection of the EOD symbol which delineates the
body of a frame from the IFR portion of the frame,
the received byte counter is compared against the
count contained in MLC[3:0]. If they match, then
the IFR will be transmitted. If they do not match,
then the TRA bit in the ERROR register is set and
no transmit attempt occurs.
– While NFL=0, an MCL[3:0] decimal value be-
tween 1 and 11 is considered valid. MCL[3:0]
values of 12, 13, 14, 15 are considered invalid
and will set the Transmit Request Aborted
(TRA) bit in the ERROR register.
– While NFL=1, an MCL[3:0] value between 1 and
15 is considered valid.
– For NFL=1 or 0, MCL[3:0] bits are don’t care dur-
ing a MSG or MSG+CRC opcode write.
– If writing an IFR opcode and MCL[3:0]=0000,
then the message length count check is ignored
(i.e. MLC=Count is disabled), and the IFR is en-
abled only on a correct CRC and a valid EOD
symbol assuming no other error conditions
(IFD, IBD, RBRK) appear.
Bit 3 = Reserved.
Bit 2:0 = OP[2:0] Transmit Opcode Select Bits.
The bits OP[2:0] form the code that the transmitter
uses to perform a transmit sequence. The codes
are listed in Table 58.
Table 58. Opcode definitions
MSG, Message Byte Opcode.
The Message byte opcode is set when the user
program wants to initiate or continue transmitting
the body of a message out the VPWO pin.
The body of a message is the string of data bytes
following an SOF symbol, but before the first EOD
symbol in a frame. If the J1850 bus is in an idle
condition when the opcode is written, an SOF
symbol is transmitted out the VPWO pin immedi-
ately before it transmits the data contained in TX-
DATA. If the JBLPD is not in idle and the J1850
transmitter has not been locked out by loss of arbi-
tration, then the TXDATA byte is transferred to the
serial output shift register for transmission immedi-
ately on completion of any previously transmitted
data. The final byte of a message string is not
transmitted using the MSG opcode (use the
MSG+CRC opcode).
Special Conditions for MSG Transmit:
– 1) A MSG cannot be queued on top of an execut-
ing IFR3 opcode. If so, then TRA is set, and
TDUF will get set because the transmit state
machine will be expecting more data, then the
inverted CRC is appended to this frame. Also,
no message byte will be sent on the next frame.
– 2) If NFL = 0 and an MSG queued without CRC
on Received Byte Count for this frame=10 will
trigger the TRA to get set, and TDUF will get set
because the state machine will be expecting
more data and the transmit machine will send
the inverted CRC after the byte which is pres-
ently transmitting. Also, no message byte will be
sent on the next frame.
Caution should be taken when TRA gets set in
these cases because the TDUF error sequence
may engage before the user program has a
chance to rewrite the TXOP register with the cor-
rect opcode. If a TDUF error occurs, a subsequent
MSG write to the TXOP register will be used as the
first byte of the next frame.
OP[2:0]
Transmit opcode
Abbreviation
000
No operation or
Cancel
CANCEL
001
Send Break Symbol
SBRK
010
Message Byte
MSG
011
Message Byte then ap-
pend CRC
MSG+CRC
100
In-Frame Response Type
1
IFR1
101
In-Frame Response Type
2
IFR2
110
In-Frame Response Type
3
IFR3
111
IFR Type 3 then append
CRC
IFR3+CRC
9



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com