ST92F124 datasheet(305/429 Pages) STMICROELECTRONICS

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J1850 Byte Level Protocol Decoder (JBLPD)

J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)

10.9.7.1 Un-Stacked Registers

STATUS REGISTER (STATUS)

R240 - Read/Write

Reset Value: 0100 0000 (40h)

The bits of this register indicate the status of the

JBLPD peripheral.

This register is forced to its reset value after the

MCU reset and while the CONTROL.JDIS bit is

set. While the CONTROL.JE bit is reset, all bits ex-

cept IDLE are forced to their reset values.

Bit 7 = ERR Error Flag.

The ERR bit indicates that one or more bits in the

ERROR register have been set. As long as any bit

in the ERROR register remains set, the ERR bit re-

mains set. When all the bits in the ERROR register

are cleared, then the ERR bit is reset by hardware.

The ERR bit is also cleared on reset or while the

CONTROL.JE bit is reset, or while the CON-

TROL.JDIS bit is set.

If the ERR_M bit of the IMR register is set, when

this bit is set an interrupt request occurs.

0: No error

1: One or more errors have occurred

Bit 6 = TRDY Transmit Ready Flag.

The TRDY bit indicates that the TXOP register is

ready to accept another opcode for transmission.

The TRDY bit is set when the TXOP register is

empty and it is cleared whenever the TXOP regis-

ter is written (by software or by DMA). TRDY will

be set again when the transmit state machine ac-

cepts the opcode for transmission.

When attempting to transmit a data byte without

using DMA, two writes are required: first a write to

TXDATA, then a write to the TXOP.

– If a byte is written into the TXOP which results in

TRA getting set, then the TRDY bit will immedi-

ately be set.

– If a TLA occurs and the opcode for which TRDY

is low is scheduled for this frame, then TRDY

will go high, if the opcode is scheduled for the

next frame, then TRDY will stay low.

– If an IBD, IFD or CRCE error condition occurs,

then TRDY will be set and any queued transmit

opcode scheduled to transmit in the present

frame will be cancelled by the JBLPD peripher-

al. A MSGx opcode scheduled to be sent in the

next frame will not be cancelled for these errors,

so TRDY would not get set.

– An RBRK error condition cancels all transmits for

this frame or any successive frames, so the

TRDY bit will always be immediately set on an

RBRK condition.

TRDY is set on reset or while CONTROL.JE is re-

set, or while the CONTROL.JDIS bit is set.

If the TRDY_M bit of the IMR register is set, when

this bit is set an interrupt request occurs.

0: TXOP register not ready to receive a new op-

code

1: TXOP register ready to receive a new opcode

Bit 5 = RDRF Receive Data Register Full Flag.

RDRF is set when a complete data byte has been

received and transferred from the serial shift regis-

ter to the RXDATA register.

RDRF is cleared when the RXDATA register is

read (by software or by DMA). RDRF is also

cleared on reset or while CONTROL.JE is reset, or

while CONTROL.JDIS bit is set.

If the RDRF_M bit of the IMR register is set, when

this bit is set an interrupt request occurs.

0: RXDATA register doesn’t contain a new data

1: RXDATA register contains a new data

Bit 4 = TLA Transmitter Lost Arbitration.

The TLA bit gets set when the transmitter loses ar-

bitration while transmitting messages or type 1

and 3 IFRs. Lost arbitration for a type 2 IFR does

not set the TLA bit. (Type 2 messages require re-

tries of the physical address if the arbitration is lost

until the frame length is reached (if NFL=0)). The

TLA bit gets set when, while transmitting a MSG,

MSG+CRC, IFR1, IFR3, or IFR3+CRC, the decod-

ed VPWI data bit symbol received does not match

the VPWO data bit symbol that the JBLPD is at-

tempting to send out. If arbitration is lost, the

VPWO line is switched to its passive state and

nothing further is transmitted until an end-of-data

(EOD) symbol is detected on the VPWI line. Also,

any queued transmit opcode scheduled for trans-

mission during this frame is cancelled (but the

TRA bit is not set).

The TLA bit can be cleared by software writing a

logic “zero” in the TLA position. TLA is also cleared

on reset or while CONTROL.JE is reset, or while

CONTROL.JDIS bit is set.

If the TLA_M bit of the IMR register is set, when

this bit is set an interrupt request occurs.

0: The JBLPD doesn’t lose arbitration

1: The JBLPD loses arbitration

ERR

TRDY

RDRF

TLA

RDT

EODM EOFM

IDLE

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