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PCF5083H/5V2/F3 数据表(PDF) 109 Page - NXP Semiconductors |
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PCF5083H/5V2/F3 数据表(HTML) 109 Page - NXP Semiconductors |
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109 / 136 page  1996 Oct 29 109 Philips Semiconductors Objective specification GSM signal processing IC PCF5083 Table 92 IOM®-2 Interface Control Register Note 1. RSTx = 0 means reset condition if either RSTO or RSTC is asserted; ‘ −’ denotes not affected from reset line. During reset (RST, RSTO, RSTC) only those registers with an explicitly given reset value are affected. All other registers are undefined and have to be set by the controller. Table 93 IOM®-2 Interface Interrupt Enable Register Note 1. RSTx = 0 means reset condition if either RSTO or RSTC is asserted; ‘ −’ denotes not affected from reset line. During reset (RST, RSTO, RSTC) only those registers with an explicitly given reset value are affected. All other registers are undefined and have to be set by the controller. BIT R/W SYMBOL OPERATION (if bit is set) RST = 0 RSTx=0(1) 0 R/W TABORT0 Monitor master 0 transmit abort request 0 − 1 R/W TABORT1 Monitor master 1 transmit abort request 0 − 2 R RABORT0 Monitor master 0 receive abort request 0 − 3 R RABORT1 Monitor master 1 receive abort request 0 − 4 R/W TEOM0 Monitor master 0 transmit end of message 0 − 5 R/W TEOM1 Monitor master 1 transmit end of message 0 − 6 R REOM0 Monitor master 0 receive end of message 0 − 7 R REOM1 Monitor master 1 receive end of message 0 − BIT R/W SYMBOL OPERATION (if bit is set) RST = 0 RSTx=0(1) 0 R/W MON0_IBF_EN Enable the MON0_IBF flag to assert the IOM_INT interrupt condition. 0 − 1 R/W MON0_OBE_EN Enable the MON0_OBE flag to assert the IOM_INT interrupt condition. 0 − 2 R/W MON1_IBF_EN Enable the MON1_IBF flag to assert the IOM_INT interrupt condition. 0 − 3 R/W MON1_OBE_EN Enable the MON1_OBE flag to assert the IOM_INT interrupt condition. 0 − 4 R/W CI0_IBF_EN Enable the CI0_IBF flag to assert the IOM_INT interrupt condition. 0 − 5 R/W CI0_OBE_EN Enable the CI0_OBE flag to assert the IOM_INT interrupt condition. 0 − 6 R/W CI1_IBF_EN Enable the CI1_IBF flag to assert the IOM_INT interrupt condition. 0 − 7 R/W CI1_OBE_EN Enable the CI1_OBE flag to assert the IOM_INT interrupt condition. 0 − |
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