S12SCIV2SLASHD datasheet(27/130 Pages) FREESCALE

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MC9S12H256 Device User Guide — V01.18

Figure 1-3 MC9S12H256 Memory Map

Table 1-2 and Figure 1-4 show the device memory map of the MC9S12H128.

Table 1-2 Device Memory Map MC9S12H128

Address

Module

Size

(Bytes)

$0000 – $0017

CORE (Ports A, B, E, Modes, Inits, Test)

$0018 – $0019

Reserved

$001A – $001B

Device ID register (PARTID)

$001C – $001F

CORE (MEMSIZ, IRQ, HPRIO)

$0020 – $0027

Reserved

$0028 – $002F

CORE (Background Debug Mode)

$0030 – $0033

CORE (PPAGE, Port K)

$0034 – $003F

Clock and Reset Generator (PLL, RTI, COP)

$0040 – $006F

Standard Timer Module 16-bit 8 channels (TIM)

$0070 – $007F

Reser

$0080 – $00AF

Analog to Digital Con

ter 10-bit 16 channels (ATD)

$00B0 – $00BF

Reser

$00C0 – $00C7

Inter Integ

$0000

$FFFF

$C000

$8000

$4000

$0400

$0800

$1000

$FF00

EXT

NORMAL

SINGLE CHIP

EXPANDED*

SPECIAL

SINGLE CHIP

VECTORS

$FF00

$FFFF

BDM

(If Active)

$C000

$FFFF

16K Fixed Flash EEPROM

2K, 4K, 8K or 16K Protected Boot Sector

$8000

$BFFF

16K Page Window

Sixteen * 16K Flash EEPROM Pages

$4000

$7FFF

16K Fixed Flash EEPROM

0.5K, 1K, 2K or 4K Protected Sector

$1000

$3FFF

$0000

$0FFF

4K Bytes EEPROM

Mappable to any 4K Boundary

$0000

$03FF

1K Register Space

Mappable to any 2K Boundary

Mappable to any 16K Boundary

12K Bytes RAM

Alignable to top ($1000 – $3FFF)

or bottom ($0000 – $2FFF)

initially overlapped by register space

* Assuming that a ‘0’ was driven onto port K7 during reset to normal expanded mode

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