S12SCIV2SLASHD datasheet(83/130 Pages) FREESCALE

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MC9S12H256 Device User Guide — V01.18

Section 6 HCS12 Core Block Description

Consult the HCS12 Core User Guide for information about the HCS12 core modules, i.e. central

processing unit (CPU), interrupt module (INT), module mapping control module (MMC), multiplexed

external bus interface (MEBI), breakpoint module (BKP) and background debug mode module (BDM).

Section 7 Clock and Reset Generator (CRG) Block

Description

Consult the CRG Block User Guide for information about the Clock and Reset Generator module.

7.1 Device-specific information

7.1.1 XCLKS

The XCLKS input signal is active high (see 2.3.10 PE7 / FP22 / XCLKS / NOACC — Port E I/O Pin 7).

Section 8 Timer (TIM) Block Description

Consult the TIM_16B8C Block User Guide for information about the Timer module.

Section 9 Analog to Digital Converter (ATD) Block

Description

Consult the ATD_10B16C Block User Guide for information about the Analog to Digital Converter

module.

Section 10 Inter-IC Bus (IIC) Block Description

Consult the IIC Block User Guide for information about the Inter-IC Bus module.

Section 11 Serial Communications Interface (SCI) Block

Description

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S12SCIV2/D 数据表(PDF) 83 Page - Freescale Semiconductor, Inc