S12SCIV2SLASHD datasheet(18/130 Pages) FREESCALE

18 / 130 page

MC9S12H256 Device User Guide — V01.18

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BDM (Background Debug Mode)

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CRG (low current oscillator, PLL, reset, clocks, COP watchdog, real time interrupt, clock monitor)

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8-bit and 4-bit ports with interrupt functionality

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Digital filtering

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Programmable rising or falling edge trigger

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Memory

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128K, 256K Flash EEPROM

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2K, 4K byte EEPROM

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6K, 12K byte RAM

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Analog-to-Digital Converter

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8, 16 channels, 10-bit resolution

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External conversion trigger capability

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Two 1M bit per second, CAN 2.0 A, B software compatible modules

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Five receive and three transmit buffers

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Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8x8bit

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Four separate interrupt channels for Rx, Tx, error and wake-up

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Low-pass filter wake-up function

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Loop-back for self test operation

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Timer

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16-bit main counter with 7-bit prescaler

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8 programmable input capture or output compare channels

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Two 8-bit or one 16-bit pulse accumulators

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2, 6 PWM channels

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Programmable period and duty cycle

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8-bit 2, 6-channel or 16-bit 1, 3-channel

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Separate control for each pulse width and duty cycle

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Center-aligned or left-aligned outputs

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Programmable clock select logic with a wide range of frequencies

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Fast emergency shutdown input

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Serial interfaces

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Two asynchronous Serial Communications Interfaces (SCI)

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Synchronous Serial Peripheral Interface (SPI)

Freescale Semiconductor, Inc.

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