S12SCIV2SLASHD datasheet(62/130 Pages) FREESCALE

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MC9S12H256 Device User Guide — V01.18

2.3.15 PE2 / FP20 / R/W — Port E I/O Pin 2

PE2 is a general purpose input or output pin. It can be configured as frontplane segment driver output FP20

of the LCD module. In MCU expanded modes of operations, this pin performs the read/write output signal

for the external bus. It indicates the direction of data on the external bus.

2.3.16 PE1 / IRQ — Port E Input Pin 1

PE1 is a general purpose input pin and also the maskable interrupt request input that provides a means of

applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.

2.3.17 PE0 / XIRQ — Port E Input Pin 0

PE0 is a general purpose input pin and also the non-maskable interrupt request input that provides a means

of applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.

2.3.18 PH[7:0] / KWH[7:0] — Port H I/O Pins [7:0]

PH7-PH0 are general purpose input or output pins. They can be configured to generate an interrupt causing

the MCU to exit STOP or WAIT mode.

NOTE:

These pins are not available in the 112-pin LQFP version.

2.3.19 PJ[3:0] / KWJ[3:0] — Port J I/O Pins [3:0]

PJ3-PJ0 are general purpose input or output pins. They can be configured to generate an interrupt causing

the MCU to exit STOP or WAIT mode.and are shared with the interrupt function.

NOTE:

These pins are not available in the 112-pin LQFP version.

2.3.20 PK7 / FP23 / ECS / ROMONE — Port K I/O Pin 7

PK7 is a general purpose input or output pin. It can be configured as frontplane segment driver output FP23

of the LCD module. During MCU expanded modes of operation, this pin is used as the emulation chip

select signal (ECS). During reset of the MCU to normal expanded modes of operation, this pin is used to

enable the Flash EEPROM memory in the memory map (ROMONE). At the rising edge of RESET, the

state of this pin is latched to the ROMON bit.

2.3.21 PK[3:0] / BP[3:0] / XADDR[17:14] — Port K I/O Pins [3:0]

PK3-PK0 are general purpose input or output pins. They can be configured as backplane segment driver

outputs BP3-BP0 of the LCD module. In MCU expanded modes of operation, these pins provide the

expanded address XADDR[17:14] for the external bus.

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S12SCIV2/D 数据表(PDF) 62 Page - Freescale Semiconductor, Inc