S12SCIV2SLASHD datasheet(80/130 Pages) FREESCALE

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MC9S12H256 Device User Guide — V01.18

5.3 Effects of Reset

When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the

respective module Block User Guides for register reset states.

5.3.1 I/O pins

Refer to the HCS12 Core User Guides for mode dependent pin configuration of port A, B, E and K out of

reset.

Refer to the PIM Block User Guide for reset configurations of all peripheral module ports.

NOTE:

For devices assembled in 112-pin LQFP packages all non-bonded out pins should

be configured as outputs after reset in order to avoid current drawn from floating

inputs. Refer to Table 2-1 for affected pins.

$FFC8, $FFC9

Reserved

$FFC6, $FFC7

CRG PLL lock

I-Bit

CRGINT (LOCKIE)

$C6

$FFC4, $FFC5

CRG Self Clock Mode

I-Bit

CRGINT (SCMIE)

$C4

$FFC2, $FFC3

Reserved

$FFC0, $FFC1

IIC Bus

I-Bit

IBCR (IBIE)

$C0

$FFBE, $FFBF

Reserved

$FFBC, $FFBD

Reserved

$FFBA, $FFBB

EEPROM

I-Bit

EECTL (CCIE, CBEIE)

$BA

$FFB8, $FFB9

FLASH

I-Bit

FCTL (CCIE, CBEIE)

$B8

$FFB6, $FFB7

CAN0 wake-up

I-Bit

CAN0RIER (WUPIE)

$B6

$FFB4, $FFB5

CAN0 errors

I-Bit

CAN0RIER (CSCIE,

OVRIE)

$B4

$FFB2, $FFB3

CAN0 receive

I-Bit

CAN0RIER (RXFIE)

$B2

$FFB0, $FFB1

CAN0 transmit

I-Bit

CAN0TIER (TXEIE[2:0])

$B0

$FFAE, $FFAF

CAN1 wake-up

I-Bit

CAN0RIER (WUPIE)

$AE

$FFAC, $FFAD

CAN1 errors

I-Bit

CAN1RIER (CSCIE,

OVRIE)

$AC

$FFAA, $FFAB

CAN1 receive

I-Bit

CAN1RIER (RXFIE)

$AA

$FFA8, $FFA9

CAN1 transmit

I-Bit

CAN1TIER (TXEIE[2:0])

$A8

$FF98 to

$FFA7

Reserved

$FF96, $FF97

Motor Control Timer Overﬂow

I-Bit

MCCTL1 (MCOCIE)

$96

$FF9E to

$FF95

Reserved

$FF8C, $FF8D

PWM Emergency Shutdown

I-Bit

PWMSDN(PWMIE)

$8C

$FF80 to

$FF8B

Reserved

Table 5-1 Reset and Interrupt Vector Table

Vector Address

Interrupt Source

CCR

Mask

Local Enable

HPRIO Value

to Elevate

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