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S12SCIV2/D 数据表(PDF) 92 Page - Freescale Semiconductor, Inc |
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S12SCIV2/D 数据表(HTML) 92 Page - Freescale Semiconductor, Inc |
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92 / 130 page  MC9S12H256 Device User Guide — V01.18 A.1.6 ESD Protection and Latch-up Immunity All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body Model (HBM), the Machine Model (MM) and the Charge Device Model. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. 5. Those pins are internally clamped to VSSPLL and VDDPLL. 6. This pin is clamped low to VSSPLL, but not clamped high. This pin must be tied low in applications. Table A-2 ESD and Latch-up Test Conditions Model Description Symbol Value Unit Human Body Series Resistance R1 1500 Ω Storage Capacitance C 100 pF Number of Pulse per pin positive negative – – 3 3 Machine Series Resistance R1 0 Ω Storage Capacitance C 200 pF Number of Pulse per pin positive negative – – 3 3 Latch-up Minimum input voltage limit –2.5 V Maximum input voltage limit 7.5 V Table A-3 ESD and Latch-Up Protection Characteristics Num C Rating Symbol Min Max Unit 1 C Human Body Model (HBM) VHBM 2000 – V 2 C Machine Model (MM) VMM 200 – V 3 C Charge Device Model (CDM) VCDM 500 – V 4C Latch-up Current at TA = 125°C positive negative ILAT +100 –100 –mA 5C Latch-up Current at TA = 27°C positive negative ILAT +200 –200 –mA Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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