S12SCIV2SLASHD datasheet(60/130 Pages) FREESCALE

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MC9S12H256 Device User Guide — V01.18

2.3 Detailed Signal Descriptions

2.3.1 EXTAL, XTAL — Oscillator Pins

EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived

from the EXTAL input frequency. XTAL is the crystal output.

2.3.2 RESET — External Reset Pin

An active low bidirectional control signal, it acts as an input to initialize the MCU to a known start-up

state, and an output when an internal MCU function causes a reset.

2.3.3 TEST — Test Pin

This pin is reserved for test.

NOTE:

The TEST pin must be tied to VSS in all applications.

2.3.4 XFC — PLL Loop Filter Pin

Dedicated pin used to create the PLL loop filter.

2.3.5 BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin

The BKGD/TAGHI/MODC pin is used as a pseudo-open-drain pin for the background debug

communication. In MCU expanded modes of operation when instruction tagging is on, an input low on

this pin during the falling edge of E-clock tags the high half of the instruction word being read into the

instruction queue. It is used as a MCU operating mode select pin during reset. The state of this pin is

latched to the MODC bit at the rising edge of RESET.

2.3.6 PAD[15:8] / AN[15:8] — Port AD Input Pins [15:8]

PAD15-PAD8 are general purpose input pins and analog inputs for the analog to digital converter.

NOTE:

These pins are not available in the 112-pin LQFP version.

2.3.7 PAD[7:0] / AN[7:0] — Port AD Input Pins [7:0]

PAD7-PAD0 are general purpose input pins and analog inputs for the analog to digital converter.

2.3.8 PA[7:0] / FP[15:8] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins

PA7-PA0 are general purpose input or output pins. They can be configured as frontplane segment driver

outputs FP15-FP8 of the LCD. In MCU expanded modes of operation, these pins are used for the

multiplexed external address and data bus.

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