S12SCIV2SLASHD datasheet(85/130 Pages) FREESCALE

85 / 130 page

MC9S12H256 Device User Guide — V01.18

There are two MSCAN modules (CAN0 and CAN1) implemented on the MC9S12H256 device. Consult

the MSCAN Block User Guide for information on each MSCAN.

Section 19 PWM Motor Control (MC) Block Description

Consult the MC_10B12C Block User Guide for information about the PWM Motor Control module.

Section 20 Port Integration Module (PIM) Block Description

Consult the PIM_9H256 Block User Guide for information about the Port Integration Module.

Section 21 Voltage Regulator (VREG) Block Description

Consult the VREG Block User Guide for information about the dual output linear voltage regulator.

21.1 Device-specific information

21.1.1 VREGEN

There is no VREGEN pin implemented on this device.

21.1.2 Modes of Operation

21.1.2.1 Run Mode

VREG enters run mode whenever the CPU is neither in Stop nor in Pseudo Stop mode. Both regulating

loops operate in Run mode with full performance.

21.1.2.2 Standby Mode

VREG enters Standby mode when the CPU operates either in Stop or in Pseudo Stop mode. The supply of

the core logic as well as the oscillators are derived from two voltage clamps. Standby mode minimizes

quiescent current drawn by the voltage regulator block.

21.1.2.3 Shutdown Mode

VREG Shutdown mode is not available on MC9S12H family devices.

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S12SCIV2/D 数据表(PDF) 85 Page - Freescale Semiconductor, Inc