S12SCIV2SLASHD datasheet(75/130 Pages) FREESCALE

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MC9S12H256 Device User Guide — V01.18

4.2.2.1 Special Single-Chip Mode

When the MCU is reset in this mode, the background debug mode is enabled and active. The MCU does

not fetch the reset vector and execute application code as it would in other modes. Instead the active

background mode is in control of CPU execution and BDM firmware is waiting for additional serial

commands through the BKGD pin. When a serial command instructs the MCU to return to normal

execution, the system will be configured as described below unless the reset states of internal control

registers have been changed through background commands after the MCU was reset.

There is no external expansion bus after reset in this mode. Ports A and B are initially simple bidirectional

I/O pins that are configured as high-impedance inputs with internal pull-ups disabled; however, writing to

the mode select bits in the MODE register (which is allowed in special modes) can change this after reset.

All of the Port E pins (except PE4/ECLK) are initially configured as general purpose high-impedance

inputs with pull-ups enabled. PE4/ECLK is configured as the E clock output in this mode.

The pins associated with Port E bits 6, 5, 3, and 2 cannot be configured for their alternate functions IPIPE1,

IPIPE0, LSTRB, and R/W while the MCU is in single chip modes. In single chip modes, the associated

control bits PIPOE, LSTRE and RDWE are reset to zero. Writing the opposite value into these bits in

single chip mode does not change the operation of the associated Port E pins.

Port E, bit 4 can be configured for a free-running E clock output by clearing NECLK=0. Typically the only

use for an E clock output while the MCU is in single chip modes would be to get a constant speed clock

for use in the external application system.

4.2.2.2 Special Test Mode (Motorola Use Only)

In expanded wide modes, Ports A and B are configured as a 16-bit multiplexed address and data bus and

Port E provides bus control and status signals. In special test mode, the write protection of many control

bits is lifted so that they can be thoroughly tested without needing to go through reset.

4.2.3 Test Operating Mode (Motorola Use Only)

There is a test operating mode in which an external master, such as an I.C. tester, can control the on-chip

peripherals.

4.2.3.1 Peripheral Mode

This mode is intended for Motorola factory testing of the MCU. In this mode, the CPU is inactive and an

external (tester) bus master drives address, data and bus control signals in through Ports A, B and E. In

effect, the whole MCU acts as if it was a peripheral under control of an external CPU. This allows faster

testing of on-chip memory and peripherals than previous testing methods. Since the mode control register

is not accessible in peripheral mode, the only way to change to another mode is to reset the MCU into a

different mode. Background debugging should not be used while the MCU is in special peripheral mode

as internal bus conflicts between BDM and the external master can cause improper operation of both

functions.

Freescale Semiconductor, Inc.

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