S12SCIV2SLASHD datasheet(72/130 Pages) FREESCALE

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MC9S12H256 Device User Guide — V01.18

even if it is located in an external slow memory device. The PE6/MODB/IPIPE1 and PE5/MODA/IPIPE0

pins act as high-impedance mode select inputs during reset.

The following paragraphs discuss the default bus setup and describe which aspects of the bus can be

changed after reset on a per mode basis.

4.2.1 Normal Operating Modes

These modes provide three operating configurations. Background debug is available in all three modes,

but must first be enabled for some operations by means of a BDM background command, then activated.

4.2.1.1 Normal Single-Chip Mode

There is no external expansion bus in this mode. All pins of Ports A, B and E are configured as general

purpose I/O pins Port E bits 1 and 0 are available as general purpose input only pins with internal pull-ups

enabled. All other pins of Port E are bidirectional I/O pins that are initially configured as high-impedance

inputs with internal pull-ups enabled. Ports A and B are configured as high-impedance inputs with their

internal pull-ups disabled.

The pins associated with Port E bits 6, 5, 3, and 2 cannot be configured for their alternate functions IPIPE1,

IPIPE0, LSTRB, and R/W while the MCU is in single chip modes. In single chip modes, the associated

control bits PIPOE, LSTRE, and RDWE are reset to zero. Writing the opposite state into them in single

chip mode does not change the operation of the associated Port E pins.

In normal single chip mode, the MODE register is writable one time. This allows a user program to change

the bus mode to narrow or wide expanded mode and/or turn on visibility of internal accesses.

Port E, bit 4 can be configured for a free-running E clock output by clearing NECLK=0. Typically the only

use for an E clock output while the MCU is in single chip modes would be to get a constant speed clock

for use in the external application system.

4.2.1.2 Normal Expanded Wide Mode

In expanded wide modes, Ports A and B are configured as a 16-bit multiplexed address and data bus and

Port E bit 4 is configured as the E clock output signal. These signals allow external memory and peripheral

devices to be interfaced to the MCU.

Port E pins other than PE4/ECLK are configured as general purpose I/O pins (initially high-impedance

inputs with internal pull-up resistors enabled). Control bits PIPOE, NECLK, LSTRE, and RDWE in the

PEAR register can be used to configure Port E pins to act as bus control outputs instead of general purpose

I/O pins.

It is possible to enable the pipe status signals on Port E bits 6 and 5 by setting the PIPOE bit in PEAR, but

it would be unusual to do so in this mode. Development systems where pipe status signals are monitored

would typically use the special variation of this mode.

The Port E bit 2 pin can be reconfigured as the R/W bus control signal by writing “1” to the RDWE bit in

PEAR. If the expanded system includes external devices that can be written, such as RAM, the RDWE bit

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