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24CSM01 数据表(PDF) 21 Page - Microchip Technology |
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24CSM01 数据表(HTML) 21 Page - Microchip Technology |
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21 / 63 page ![]() 2023 Microchip Technology Inc. and its subsidiaries Preliminary DS20006781B -page 21 24CSM01 7.3 Sequential Read A sequential read is initiated by either a current address read or a random read. After the host receives a data byte, it responds with an Acknowledge. As long as the EEPROM receives an ACK, it will continue to increment the word address and serially clock out the sequential data byte. When the maximum memory address is reached, the internal Address Pointer will automatically roll over from word address 1FFFFh to word address 00000h if the host acknowledges the byte received from word address 1FFFFh. All types of read operations will be terminated if the host does not respond with an ACK (it NACKs) during the ninth clock cycle, which will force the device into Standby mode. After the NACK response, the host may send a Stop condition to complete the protocol, or it can send a Start condition to begin the next sequence. FIGURE 7-3: SEQUENTIAL READ SCL MSb MSb MSb SDA 123 45 6 7 8 9 12 3 4 5 6 7 8 9 1 2 3 45 6 7 8 9 Word Address – Byte 1 Word Address – Byte 0 Device Address Byte 10 1 0 0 0 A15 A14 A13 A12 A11 A10 A9 A8 0 A7 A6 A5 A4 A3 A2 0 A1 A0 A2 A1 A16 ACK from Client ACK from Client ACK from Client Start by Host MSb MSb MSb 123 45 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 45 6 7 8 9 Data Byte (n+1) Data Byte (n) Device Address Byte 1 010 0 1 D7 D6 D5 D4 D3 D2 D1 D0 0 D7 D6 D5 D4 D3 D2 0 D1 D0 A2 A1 x ACK from Host ACK from Host ACK from Client Start by Host MSb MSb MSb 1 2 34 5 6 7 8 91 2 3 4 5 6 7 8 9 12 34 5 6 7 8 9 Data Byte (n+x) Data Byte (n+3) Device Byte (n+2) D7 D6 D5 D4 0 D0 D7 D6 D5 D4 D3 D2 D1 D0 0 D7 D6 D5 D4 D3 D2 1 D1 D0 D3 D2 D1 NACK from Host ACK from Host ACK from Host Stop by Host Note 1: “Don’t care” bit. (1) Start by Host |
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