24CSM01 datasheet(13/63 Pages) MICROCHIP

13 / 63 page

 2023 Microchip Technology Inc. and its subsidiaries

Preliminary

DS20006781B

-page 13

24CSM01

FIGURE 5-2:

ACKNOWLEDGE TIMING

5.6

Standby Mode

The 24CSM01 features a low-power Standby mode,

which is enabled when any one of the following occurs:

• A valid power-up sequence is performed (see

Section 1.1 “Power-Up Requirements and

Reset Behavior”).

• A Stop condition at the end of a valid I2C

transaction is received by the device unless it

initiates an internal write cycle (see Section 6.0

“Write Operations”).

• At the completion of an internal write cycle (see

Section 6.0 “Write Operations”).

• An unsuccessful match of the device type

identifier or hardware client address in the device

address byte occurs (see Section 3.3 “Device

Addressing”).

• The host does not acknowledge the receipt of a

data readout from the device; instead, it sends a

NACK response (see Section 7.0 “Read

Operations”).

5.7

Software Reset

After an interruption in protocol, power loss or system

Reset, any Two-Wire device can be protocol Reset by

clocking SCL until SDA is released by the EEPROM

and goes high. The number of clock cycles until SDA is

released by the EEPROM will vary. The Software Reset

sequence should not take more than nine dummy clock

cycles. Note that the Software Reset sequence will not

interrupt the internal write cycle and only resets the I2C

interface.

Once the Software Reset sequence is complete, a new

protocol can be sent to the device by sending a Start

condition followed by the protocol. Figure 5-3 illustrates

the Software Reset sequence.

In the event that the device is still non-responsive or

remains active on the SDA bus, a power cycle must be

used to reset the device (see Section 1.1.1 “Device

Reset”).

FIGURE 5-3:

SOFTWARE RESET

SCL

Transmitter must release the SDA line at this point,

allowing the Receiver to pull the SDA line low to

acknowledge the previous eight bits of data.

Receiver must release the SDA line

at this point, so the Transmitter can

continue sending data.

Data from Transmitter

SDA

Acknowledge

Bit

Data from Transmitter

SCL

SDA

SDA Released

by EEPROM

Device is

Software Reset

389

Dummy Clock Cycles

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