24CSM01 datasheet(14/63 Pages) MICROCHIP

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24CSM01

DS20006781B

-page 14

Preliminary

 2023 Microchip Technology Inc. and its subsidiaries

6.0

WRITE OPERATIONS

All write operations for the 24CSM01 begin with the

host sending a Start condition followed by a device

address byte with the R/W bit set to a logic ‘0’ and then

by the word address bytes. The data value(s) to be

written to the device immediately follow the word

address bytes.

6.1

Byte Write

The 24CSM01 supports the writing of a single 8-bit

byte. Selecting a data byte in the 24CSM01 requires a

17-bit word address.

Upon receipt of the proper device address and the

word address bytes, the EEPROM will send an

Acknowledge. The device will then be ready to receive

the 8-bit data byte. Following the receipt of the data

byte, the EEPROM will respond with an Acknowledge.

The addressing device, such as a host, must then

terminate the write operation with a Stop condition. At

that time, the EEPROM will enter an internally

self-timed write cycle, which will be completed within

TWC, while the data byte is being programmed into the

nonvolatile EEPROM. All inputs are disabled during

this write cycle and the EEPROM will not respond until

the write operation is complete.

If an attempt is made to write to a write-protected

portion of the array, no data will be written and the

device will immediately accept a new command.

FIGURE 6-1:

BYTE WRITE

SCL

MSb

A1 A16

A15 A14

A12 A11 A10 A9

A13

SDA

MSb

A1 A0

D3 D2

D1 D0

MSb

Device Address Byte

Word Address – Byte 0

ACK

from

Client

ACK

from

Client

Start

Host

Data Byte

Word Address – Byte 1

ACK

from

Client

ACK

from

Client

Stop

Host

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