24CSM01 datasheet(17/63 Pages) MICROCHIP

17 / 63 page

 2023 Microchip Technology Inc. and its subsidiaries

Preliminary

DS20006781B

-page 17

24CSM01

6.5

Acknowledge Polling

Since the device will not acknowledge during a write

cycle, Acknowledge polling can be used to determine

when the cycle is complete (this feature can be used to

maximize bus throughput). Once the Stop condition for a

write operation has been issued from the host, the

device initiates the internally timed write cycle. ACK

polling can be initiated immediately. This involves the

host sending a Start condition followed by the device

address byte for a write operation (R/W = ‘0’). If the

device is still busy with the write cycle, then a NACK will

be returned. If a NACK is returned, then the Start

condition and device address byte must be resent. If the

cycle is complete, then the device will return the ACK

and the host can then proceed with the next read or write

operation. See Figure 6-4 for flow diagram.

FIGURE 6-4:

ACKNOWLEDGE

POLLING FLOW

6.6

Write Protection

The 24CSM01 can be set in two different Write

Protection modes. The selection between the two

modes is controlled by the Configuration register

EWPM bit. When this bit is a logic ‘0’, the device is set

in Legacy Hardware Write Protection mode and when

the bit is a logic ‘1’, the device is set for Enhanced

Software Write Protection mode.

6.6.1

LEGACY HARDWARE WRITE

PROTECTION MODE

When the EWPM bit is set to logic ‘0’, the 24CSM01

utilizes a legacy hardware data protection scheme that

allows the user to write-protect the entire memory

contents when the WP pin is asserted (high). No write

protection will be set if the WP pin is deasserted (low).

6.6.1.1

Write-Protect Pin Timing

The status of the WP pin is sampled at the Stop

condition for every byte write or page write operation

prior to the start of an internally self-timed write

operation (see Figure 1-1). Changing the WP pin state

after the Stop condition has been sent will not alter or

interrupt the execution of the write cycle.

If an attempt is made to write to the device while the

WP pin has been asserted, the device will

acknowledge the device address, word address and

data bytes, but no write cycle will occur when the Stop

condition is issued and the device will immediately be

ready to accept a new read or write operation.

Note:

Polling, while operating in High-Speed

mode, is not supported on the 24CSM01.

Therefore, polling must occur while using

Fast mode plus (1 MHz) or slower clock

frequencies.

Send

Write Operation

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Device Address Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

Operation

Yes

Note:

Writing to the Security register can be

inhibited by asserting the Write-Protect

pin regardless of the state of the EWPM

bit. Writing to the Configuration register

cannot be inhibited by asserting the

Write-Protect pin.

TABLE 6-1:

LEGACY HARDWARE WRITE

PROTECTION BEHAVIOR

WP Pin

Protected Address Range

1 (high)

Full Array (00000h-1FFFFh)

0 (low)

None

24CSM01 数据表(PDF) 17 Page - Microchip Technology

24CSM01 数据表(HTML) 17 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

数据表下载