24CSM01 datasheet(11/63 Pages) MICROCHIP

11 / 63 page

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Preliminary

DS20006781B

-page 11

24CSM01

3.3.1.1

Read/Write Select Bit

The eighth bit (bit 0) of the device address byte is the

Read/Write Select (R/W) bit. A read operation is

initiated if this bit is a logic ‘1’ and a write operation is

initiated if this bit is a logic ‘0’.

Upon the successful comparison of the device address

byte, the 24CSM01 will respond. If a valid comparison

is not made, the device will not respond and will return

to a standby state.

3.3.2

WORD ADDRESS BYTES

Two 8-bit word address bytes are transmitted to the

device immediately following the device address byte.

The first word address byte contains the eight Most

Significant bits (MSbs) of the 17-bit memory array word

address to specify which location in the EEPROM to

start reading or writing. When accessing the Security

address be set to a logic ‘0’ and the A11 and A10 bits

be set to ‘10b’, respectively. When accessing the

Configuration register, it is required that the A15 bit of

the first word address be set to a logic ‘1’ and the A11

and A10 bits be set to ‘10b’, respectively. Refer to

Table 3-3 for details.

Next, the second word address byte is sent to the

device, which provides the remaining eight bits of the

word address (A7 through A0). Refer to Table 3-4 for

details.

TABLE 3-3:

FIRST WORD ADDRESS BYTE

Memory Region

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1-Mbit EEPROM

A15

A14

A13

A12

A11

A10

Security Register Read/Write

Lock Security Register

Configuration Register

TABLE 3-4:

SECOND WORD ADDRESS BYTE

Memory Region

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1-Mbit EEPROM

Security Register Read/Write

Lock Security Register(1)

Configuration Register(1)

Note 1: When accessing the Configuration register or locking the Security register, the second word address byte

must be transmitted to the device, despite containing only “don’t care” values.

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