24CSM01 datasheet(16/63 Pages) MICROCHIP

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24CSM01

DS20006781B

-page 16

Preliminary

 2023 Microchip Technology Inc. and its subsidiaries

6.3

Internal Writing Methodology

The 24CSM01 incorporates a built-in Error Correction

Code (ECC) logic scheme. The EEPROM array is

internally organized as a group of four connected 8-bit

bytes, plus an additional six ECC (Error Correction

Code) bits of EEPROM. These 38 bits are referred to as

the internal physical data word. During a read operation,

the ECC logic compares each 4-byte physical data word

with its corresponding six ECC bits. If a single bit out of

the 4-byte region reads incorrectly, the ECC logic will

detect the bad bit and replace it with the correct value

before the data are serially clocked out. This architecture

significantly improves the reliability of the 24CSM01

compared to an implementation that does not utilize

ECC.

It is important to note that data are always physically

written to the part at the internal physical data word level

regardless of the number of bytes written. Writing single

bytes is still possible with the byte write operation but,

internally, the other three bytes within that 4-byte

location where the single byte was written, along with the

six ECC bits, will be updated.

Due to this architecture, the write endurance is rated at

the internal physical data word level (4-byte word).

The system designer needs to optimize the application

writing algorithms to observe these internal word

boundaries to reach the write cycle endurance rating.

6.4

Write Cycle Timing

The length of the self-timed write cycle, or TWC, is

defined as the amount of time from the Stop condition

that begins the internal write operation to the Start

condition of the first device address byte sent to the

24CSM01 that it subsequently responds to with an

ACK (see Figure 6-3).

During the internally self-timed write cycle, any

attempts to access the device will be ignored.

FIGURE 6-3:

WRITE CYCLE TIMING

TWC

Stop

Condition

Start

Condition

Data Word n

ACK

SDA

Stop

Condition

SCL

ACK

First Acknowledge from the device to

a valid device address sequence after

write cycle is initiated. The minimum

Twc can only be determined through

the use of an ACK polling routine.

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