24CSM01 datasheet(22/63 Pages) MICROCHIP

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24CSM01

DS20006781B

-page 22

Preliminary

 2023 Microchip Technology Inc. and its subsidiaries

8.0

HIGH-SPEED MODE

The 24CSM01 supports the I2C High-Speed (HS)

mode, allowing it to operate at clock frequencies up to

3.4 MHz for read and write operations.

To place the 24CSM01 into HS mode, the host must

first initiate a Start condition, followed by the reserved

HS mode host code of ‘00001xxxb’ (Table 8-1).

The HS mode host code must be sent to the device at

Fast mode plus (1 MHz) or slower clock frequencies.

Since the HS mode host code is meant to be

recognized by all client devices that support the HS

mode, the 24CSM01 will not acknowledge (NACK) the

HS mode host code.

Once the 24CSM01 receives the HS mode host code

and the NACK occurs, the 24CSM01 will relax its input

filters on SDA and SCL to the HS mode tolerance to

accept transfers, at up to 3.4 MHz. The device will then

enter HS mode and wait for a Repeated Start condition

before the next operation can occur.

Next, the host must issue a Start condition, followed by

a valid device address byte to which the device will

ACK. The host can continue with read or write

operations at the higher clock speed and the 24CSM01

will continue to operate in the HS mode until one of the

following events occurs:

• The host sends a Stop condition. Therefore, the

host should use a Repeated Start condition to

begin new HS mode operations rather than a

Stop-Start sequence.

• A Power-on-Reset (POR) event occurs.

Once the 24CSM01 exits the HS mode from one of

these events, the device will switch its input and output

filters back to the standard I2C (Legacy) mode.

Figure 8-1 illustrates the HS mode entry sequence.

FIGURE 8-1:

HIGH-SPEED MODE ENTRY SEQUENCE

TABLE 8-1:

HIGH-SPEED MODE HOST CODE

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0

ACK Bit

00001xxx

NACK from Clients

Note:

The internal write cycle requires a Stop

condition to be sent after the last data

byte. This Stop condition will cause the

24CSM01 to exit HS mode. Therefore, if

more than one page of data is to be

written, HS mode must be re-entered for

every write operation.

Note:

High-Speed mode entry is ignored during

a write cycle. Therefore, polling must

occur while using Fast mode plus (1 MHz)

or slower clock frequencies. Refer to

Section 6.5 “Acknowledge Polling” for

additional information. High-Speed mode

can be re-entered after the write cycle has

completed.

SCL

345

678

SDA

MSb

Host Code

1xx

Repeated

Start by

Host

NACK

from

Client(s)

Start

Host

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