ENC28J60-CSLASHML datasheet(24/96 Pages) MICROCHIP

24 / 96 page

ENC28J60

DS39662B-page 22

Preliminary

3.3.4

PHSTAT REGISTERS

The PHSTAT1 and PHSTAT2 registers contain read-

only bits that show the current status of the PHY

module’s operations, particularly the conditions of the

communications link to the rest of the network.

The PHSTAT1 register (Register 3-5) contains the

LLSTAT bit; it clears and latches low if the physical

layer link has gone down since the last read of the

used to determine exactly when the link fails. It may be

particularly useful if the link change interrupt is not

used.

The PHSTAT1 register also contains a jabber status bit.

An Ethernet controller is said to be “jabbering” if it con-

tinuously transmits data without stopping and allowing

other nodes to share the medium. Generally, the jabber

condition indicates that the local controller may be

grossly violating the maximum packet size defined by

the IEEE specification. This bit latches high to indicate

that a jabber condition has occurred since the last read

of the register.

The PHSTAT2 register (Register 3-6) contains status

bits which report if the PHY module is linked to the

network and whether or not it is transmitting or

receiving.

3.3.5

PHID1 AND PHID2 REGISTERS

The PHID1 and PHID2 registers are read-only

registers. They hold constant data that help identify the

Ethernet controller and may be useful for debugging

purposes. This includes:

• The part number of the PHY module

(PPN5:PPN0)

• The revision level of the PHY module

(PREV3:PREV0); and

• The PHY Identifier, as part of Microchip’s

corporate Organizationally Unique Identifier (OUI)

(OUI3:OUI24)

The PHY part number and revision are part of PHID2.

The upper two bytes of the PHY identifier are located in

PHID1, with the remainder in PHID2. The exact

locations within registers are shown in Table 3-3.

The 22 bits of the OUI contained in the PHY Identifier

(OUI3:OUI24, corresponding to PHID1<15:0> and

PHID2<15:10>) are concatenated with ‘00’ as the first

two digits (OUI1 and OUI2) to generate the entire OUI.

For convenience, this 24-bit string is usually interpreted

in hexadecimal; the resulting OUI for Microchip Tech-

nology is 0004A3h.

Revision information is also stored in EREVID. This is

a read-only control register which contains a 5-bit

identifier for the specific silicon revision level of the

device. Details of this register are shown in Table 3-2.

ENC28J60-C/ML 数据表(PDF) 24 Page - Microchip Technology

ENC28J60-C/ML 数据表(HTML) 24 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

数据表下载