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ENC28J60-C/ML 数据表(PDF) 25 Page - Microchip Technology

部件名 ENC28J60-C/ML
功能描述  Stand-Alone Ethernet Controller with SPI Interface
PDF  96 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

ENC28J60-C/ML 数据表(HTML) 25 Page - Microchip Technology

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© 2006 Microchip Technology Inc.
Preliminary
DS39662B-page 23
ENC28J60
REGISTER 3-5:
PHSTAT1: PHYSICAL LAYER STATUS REGISTER 1
U-0
U-0
U-0
R-1
R-1
U-0
U-0
U-0
—
—
—PFDPX
PHDPX
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
R/LL-0
R/LH-0
U-0
—
—
—
—
—
LLSTAT
JBSTAT
—
bit 7
bit 0
Legend:
‘1’ = Bit is set
R = Read-only bit
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n = Value at POR
R/L = Read-only latch bit
LL = Bit latches low
LH = Bit latches high
bit 15-13
Unimplemented: Read as ‘0’
bit 12
PFDPX: PHY Full-Duplex Capable bit
1
= PHY is capable of operating at 10 Mbps in Full-Duplex mode (this bit is always set)
bit 11
PHDPX: PHY Half-Duplex Capable bit
1
= PHY is capable of operating at 10 Mbps in Half-Duplex mode (this bit is always set)
bit 10-3
Unimplemented: Read as ‘0’
bit 2
LLSTAT: PHY Latching Link Status bit
1
= Link is up and has been up continously since PHSTAT1 was last read
0
= Link is down or was down for a period since PHSTAT1 was last read
bit 1
JBSTAT: PHY Latching Jabber Status bit
1
= PHY has detected a transmission meeting the jabber criteria since PHSTAT1 was last read
0
= PHY has not detected any jabbering transmissions since PHSTAT1 was last read
bit 0
Unimplemented: Read as ‘0’



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