ENC28J60-CSLASHML datasheet(5/96 Pages) MICROCHIP

5 / 96 page

Preliminary

DS39662B-page 3

ENC28J60

1.0

OVERVIEW

The ENC28J60 is a stand-alone Ethernet controller

with an industry standard Serial Peripheral Interface

(SPI). It is designed to serve as an Ethernet network

interface for any controller equipped with SPI.

The ENC28J60 meets all of the IEEE 802.3 specifica-

tions. It incorporates a number of packet filtering

schemes to limit incoming packets. It also provides an

internal DMA module for fast data throughput and hard-

ware assisted checksum calculation, which is used in

various network protocols. Communication with the

host controller is implemented via an interrupt pin and

the SPI, with clock rates of up to 20 MHz. Two dedi-

cated pins are used for LED link and network activity

indication.

A simple block diagram of the ENC28J60 is shown in

Figure 1-1. A typical application circuit using the device

is shown in Figure 1-2. With the ENC28J60, two pulse

transformers and a few passive components are all that

is required to connect a microcontroller to an Ethernet

network.

The ENC28J60 consists of seven major functional

blocks:

An SPI interface that serves as a communica-

tion channel between the host controller and the

ENC28J60.

Control Registers which are used to control and

monitor the ENC28J60.

A dual port RAM buffer for received and

transmitted data packets.

An arbiter to control the access to the RAM

buffer when requests are made from DMA,

transmit and receive blocks.

The bus interface that interprets data and

commands received via the SPI interface.

The MAC (Medium Access Control) module that

implements IEEE 802.3 compliant MAC logic.

The PHY (Physical Layer) module that encodes

and decodes the analog data that is present on

the twisted pair interface.

The device also contains other support blocks, such as

the oscillator, on-chip voltage regulator, level translators

to provide 5V tolerant I/Os and system control logic.

FIGURE 1-1:

ENC28J60 BLOCK DIAGRAM

Dual Port RAM

8 Kbytes

DMA &

Checksum

TXBM

RXBM

Arbiter

Flow Control

Host Interface

Control

Registers

25 MHz

Power-on

PHY

Bus Interface

SPI

MII

Interface

MIIM

Interface

TPOUT+

TPOUT-

TPIN+

TPIN-

RBIAS

OSC1

OSC2

Voltage

System Control

CS(1)

SI(1)

SCK(1)

INT

VCAP

CLKOUT

LEDA

LEDB

RESET(1)

RXF (Filter)

MAC

ch0

ch1

ch0

ch1

Buffer

Note 1:

These pins are 5V tolerant.

Regulator

Reset

Oscillator

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