ENC28J60-CSLASHML datasheet(62/96 Pages) MICROCHIP

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ENC28J60

DS39662B-page 60

Preliminary

11.1

Power-on Reset (POR)

A Power-on

Reset

pulse

generated on-chip

whenever VDD rises above a certain threshold. This

allows the device to start in the initialized state when

VDD is adequate for operation.

The POR circuitry is always enabled. As a result, most

applications do not need to attach any external circuitry

to the RESET pin to ensure a proper Reset at power-

up. The RESET pin’s internal weak pull-up will maintain

a logical high level on the pin during normal device

operation.

To ensure proper POR operation, a minimum rise rate

for VDD is specified (parameter D003). The application

circuit must meet this requirement to allow the Oscillator

Start-up Timer and CLKOUT functions to reset properly.

After a Power-on Reset, the contents of the dual port

buffer memory will be unknown. However, all registers

will be loaded with their specified Reset values. Certain

portions of the ENC28J60 must not be accessed

immediately after a POR. See Section 2.2 “Oscillator

Start-up Timer” for more information.

11.2

System Reset

The System Reset of ENC28J60 can be accomplished

by either the RESET pin, or through the SPI interface.

The RESET pin provides an asynchronous method for

triggering an external Reset of the device. A Reset is

generated by holding the RESET pin low. The

ENC28J60 has a noise filter in the RESET path which

detects and ignores small pulses of time tRSTLOW or

less. When the RESET pin is held high, the ENC28J60

will operate normally.

The ENC28J60 can also be reset via the SPI using the

System Reset Command. See Section 4.0 “Serial

Peripheral Interface (SPI)”.

The RESET pin will not be driven low by any internal

Resets, including a System Reset Command via the

SPI interface.

After a System Reset, all PHY registers should not be

read or written to until at least 50

μs have passed since

the Reset has ended. All registers will revert to their

Reset default values. The dual port buffer memory will

maintain state throughout the System Reset.

11.3

Transmit Only Reset

The Transmit Only Reset is performed by writing a ‘1’ to

the TXRST bit in the ECON1 register using the SPI inter-

face. If a packet was being transmitted when the TXRST

bit was set, the hardware will automatically clear the

TXRTS bit and abort the transmission. This action resets

the transmit logic only. The System Reset automatically

performs the Transmit Only Reset. Other register and

control blocks, such as buffer management and host

interface, are not affected by a Transmit Only Reset

event. When the host controller wishes to return to

normal operation, it should clear the TXRST bit.

11.4

Receive Only Reset

The Receive Only Reset is performed by writing a ‘1’ to

the RXRST bit in the ECON1 register using the SPI

interface. If packet reception was enabled (the RXEN

bit was set) when RXRST was set, the hardware will

automatically clear the RXEN bit. If a packet was being

received, it would be immediately aborted. This action

resets receive logic only. The System Reset automati-

cally performs Receive Only Reset. Other register and

control blocks, such as the buffer management and

host interface blocks, are not affected by a Receive

Only Reset event. When the host controller wishes to

return to normal operation, it should clear the RXRST

bit.

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