ENC28J60-CSLASHML datasheet(37/96 Pages) MICROCHIP

37 / 96 page

Preliminary

DS39662B-page 35

ENC28J60

MACON3: MAC CONTROL REGISTER 3

R/W-0

PADCFG2

PADCFG1

PADCFG0

TXCRCEN

PHDREN

HFRMEN

FRMLNEN

FULDPX

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-5

PADCFG2:PADCFG0: Automatic Pad and CRC Configuration bits

111

= All short frames will be zero padded to 64 bytes and a valid CRC will then be appended

110

= No automatic padding of short frames

101

= MAC will automatically detect VLAN Protocol frames which have a 8100h type field and auto-

matically pad to 64 bytes. If the frame is not a VLAN frame, it will be padded to 60 bytes. After

padding, a valid CRC will be appended.

100

= No automatic padding of short frames

011

= All short frames will be zero padded to 64 bytes and a valid CRC will then be appended

010

= No automatic padding of short frames

001

= All short frames will be zero padded to 60 bytes and a valid CRC will then be appended

000

= No automatic padding of short frames

bit 4

TXCRCEN: Transmit CRC Enable bit

= MAC will apend a valid CRC to all frames transmitted regardless of PADCFG. TXCRCEN must be

set if PADCFG specifies that a valid CRC will be appended.

= MAC will not append a CRC. The last 4 bytes will be checked and if it is an invalid CRC, it will be

reported in the transmit status vector.

bit 3

PHDREN: Proprietary Header Enable bit

= Frames presented to the MAC contain a 4-byte proprietary header which will not be used when

calculating the CRC

= No proprietary header is present. The CRC will cover all data (normal operation).

bit 2

HFRMEN: Huge Frame Enable bit

= Frames of any size will be allowed to be transmitted and receieved

= Frames bigger than MAMXFL will be aborted when transmitted or received

bit 1

FRMLNEN: Frame Length Checking Enable bit

= The type/length field of transmitted and received frames will be checked. If it represents a length, the

frame size will be compared and mismatches will be reported in the transmit/receive status vector.

= Frame lengths will not be compared with the type/length field

bit 0

FULDPX: MAC Full-Duplex Enable bit

= MAC will operate in Full-Duplex mode. PDPXMD bit must also be set.

= MAC will operate in Half-Duplex mode. PDPXMD bit must also be clear.

ENC28J60-C/ML 数据表(PDF) 37 Page - Microchip Technology

ENC28J60-C/ML 数据表(HTML) 37 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

数据表下载

链接网址

ENC28J60-C/ML 数据表(PDF) 37 Page - Microchip Technology

ENC28J60-C/ML 数据表(HTML) 37 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

数据表 下载

链接网址

数据表下载