ENC28J60-CSLASHML datasheet(35/96 Pages) MICROCHIP

35 / 96 page

Preliminary

DS39662B-page 33

ENC28J60

6.0

INITIALIZATION

Before the ENC28J60 can be used to transmit and

receive packets, certain device settings must be initial-

ized. Depending on the application, some configuration

options may need to be changed. Normally, these tasks

may be accomplished once after Reset and do not

need to be changed thereafter.

6.1

Receive Buffer

Before receiving any packets, the receive buffer must

be initialized by programming the ERXST and ERXND

Pointers. All memory between and including the

ERXST and ERXND addresses will be dedicated to the

receive hardware. It is recommended that the ERXST

Pointer be programmed with an even address.

Applications expecting large amounts of data and

frequent packet delivery may wish to allocate most of

the memory as the receive buffer. Applications that

may need to save older packets or have several

packets ready for transmission should allocate less

memory.

When programming the ERXST or ERXND Pointer, the

internal hardware copy of the ERXWRPT registers will

automatically be updated with the value of ERXST. This

value will be used as the starting location when the

receive hardware begins writing received data. The

ERXWRPT registers are updated by the hardware only

when a new packet is successfully received.

For tracking purposes, the ERXRDPT registers should

additionally be programmed with the same value. To

program ERXRDPT, the host controller must write to

ERXRDPTL first, followed by ERXRDPTH. See

Section 7.2.4 “Freeing Receive Buffer Space” for

more information.

6.2

Transmission Buffer

All memory which is not used by the receive buffer is

considered the transmission buffer. Data which is to be

transmitted should be written into any unused space.

After a packet is transmitted, however, the hardware

will write a seven-byte status vector into memory after

the last byte in the packet. Therefore, the host control-

ler should leave at least seven bytes between each

packet and the beginning of the receive buffer. No

explicit action is required to initialize the transmission

buffer.

6.3

Receive Filters

The appropriate receive filters should be enabled or

disabled by writing to the ERXFCON register. See

Section 8.0 “Receive Filters” for information on how

to configure it.

6.4

Waiting For OST

If the initialization procedure is being executed immedi-

ately following a Power-on Reset, the ESTAT.CLKRDY

bit should be polled to make certain that enough time

has elapsed before proceeding to modify the MAC and

PHY registers. For more information on the OST, see

Section 2.2 “Oscillator Start-up Timer”.

Note:

After writing to ERXST or ERXND, the

ERXWRPT registers are not updated

immediately; only the internal hardware

copy of the ERXWRPT registers is

updated.

Therefore,

comparing

(ERXWRPT = = ERXST) is not practical in

a firmware initialization routine.

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