ENC28J60-CSLASHML datasheet(78/96 Pages) MICROCHIP

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ENC28J60

DS39662B-page 76

Preliminary

15.1

Using the BIST

When the BIST controller is started, it will fill the entire

buffer with the data generated for the current test

configuration and it will also calculate a checksum of

the data as it is written. When the BIST is complete, the

EBSTCS registers will be updated with the checksum.

The host controller will be able to determine if the test

passed or failed by using the DMA module to calculate

a checksum of all memory. The resulting checksum

generated by the DMA should match the BIST check-

sum. If after any properly executed test, the checksums

differ, a hardware fault may be suspected.

The BIST controller supports 3 different operations:

• Random Data Fill

•Address Fill

• Pattern Shift Fill

The ports through which the BIST and DMA modules

access the dual port SRAM can be swapped for each

of the four Test modes to ensure proper read/write

capability from both ports.

To use the BIST:

Program the EDMAST register pair to 0000h.

Program EDMAND and ERXND register pairs to

1FFFh.

Configure the DMA for checksum generation by

setting CSUMEN in ECON1.

Write the seed/initial shift value byte to the

EBSTSD register (this is not necessary if

Address Fill mode is used).

Enable Test mode, select the desired test, select

the desired port configuration for the test.

Start the BIST by setting EBSTCON.BISTST.

Start the DMA checksum by setting DMAST in

ECON1. The DMA controller will read the

memory at the same rate the BIST controller will

write to it, so the DMA can be started any time

after the BIST is started.

Wait for the DMA to complete by polling the

DMAST bit or receiving the DMA interrupt (if

enabled).

Compare the EDMACS registers with the

EBSTCS registers.

To ensure full testing, the test should be redone with

the Port Select bit, PSEL, altered. When not using

Address Fill mode, additional tests may be done with

different seed values to gain greater confidence that

the memory is working as expected.

At any time during a test, the test can be canceled by

clearing the BISTST, DMAST and TME bits. While the

BIST is filling memory, the EBSTSD register should not

be accessed, nor should any configuration changes

occur. When the BIST completes its memory fill and

checksum generation, the BISTST bit will automatically

be cleared.

The BIST module requires one main clock cycle for

each byte that it writes into the RAM. The DMA mod-

ule’s checksum implementation requires the same time

but it can be started immediately after the BIST is

started. As a result, the minimum time required to do

one test pass is slightly greater than 327.68

μs.

15.2

Random Data Fill Mode

In Random Data Fill mode, the BIST controller will write

pseudo-random data into the buffer. The random data

is generated by a Linear Feedback Shift Register

(LFSR) implementation. The random number genera-

tor is seeded by the initial contents of the EBSTSD

the BIST is finished.

Because of the LFSR implementation, an initial seed of

zero will generate a continuous pattern of zeros. As a

result, a non-zero seed value will likely perform a more

extensive memory test. Selecting the same seed for

two separate trials will allow a repeat of the same test.

15.3

Address Fill Mode

In Address Fill mode, the BIST controller will write the

low byte of each memory address into the associated

buffer location. As an example, after the BIST is oper-

ated, the location 0000h should have 00h in it, location

0001h should have 01h in it, location 0E2Ah should

have 2Ah in it and so on. With this fixed memory

pattern, the BIST and DMA modules should always

generate a checksum of F807h. The host controller

may use Address Fill mode to confirm that the BIST

and DMA modules themselves are both operating as

intended.

15.4

Pattern Shift Fill Mode

In Pattern Shift Fill mode, the BIST controller writes the

value of EBSTSD into memory location 0000h. Before

writing to location 0001h, it shifts the contents of

EBSTSD to the left by the value specified by the

PSV2:PSV0 bits in EBSTCON. Bits that leave the most

significant end of EBSTSD are wrapped around to the

least significant side. This shift is repeated for each

new address. As a result of shifting the data, a checker-

board pattern can be written into the buffer memory to

confirm that adjacent memory elements do not affect

each other when accessed.

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