ENC28J60-CSLASHML datasheet(42/96 Pages) MICROCHIP

42 / 96 page

ENC28J60

DS39662B-page 40

Preliminary

FIGURE 7-2:

SAMPLE TRANSMIT PACKET LAYOUT

To achieve the example layout shown in Figure 7-2 and

to transmit a packet, the host controller should:

Appropriately program the ETXST Pointer to

point to an unused location in memory. It will

point to the per packet control byte. In the

example, it would be programmed to 0120h. It is

recommended that an even address be used for

ETXST.

Use the WBM SPI command to write the per

packet control byte, the destination address, the

source MAC address, the type/length and the

data payload.

Appropriately program the ETXND Pointer. It

should point to the last byte in the data payload.

In the example, it would be programmed to

0156h.

Clear EIR.TXIF, set EIE.TXIE and set EIE.INTIE

to enable an interrupt when done (if desired).

Start the transmission process by setting

ECON1.TXRTS.

If a DMA operation was in progress while the TXRTS bit

was set, the ENC28J60 will wait until the DMA opera-

tion is complete before attempting to transmit the

packet. This possible delay is required because the

DMA and transmission engine share the same memory

access port. Similarly, if the DMAST bit in ECON1 is set

after TXRTS is already set, the DMA will wait until the

TXRTS bit becomes clear before doing anything. While

the transmission is in progress, none of the unshaded

bits (except for the EECON1 register’s bits) in Table 7-2

should be changed. Additionally, none of the bytes to be

transmitted should be read or written to through the SPI.

If the host controller wishes to cancel the transmission,

it can clear the TXRTS bit.

When the packet is finished transmitting or was aborted

due to an error/cancellation, the ECON1.TXRTS bit will

be cleared, a seven-byte transmit status vector will be

written to the location pointed to by ETXND + 1, the

EIR.TXIF will be set and an interrupt will be generated

(if enabled). The ETXST and ETXND Pointers will not

be modified. To check if the packet was successfully

transmitted, the ESTAT.TXABRT bit should be read. If

it was set, the host controller may interrogate the

ESTAT.LATECOL bit in addition to the various fields in

the transmit status vector to determine the cause. The

transmit status vector is organized as shown in

Table 7-1. Multi-byte fields are written in little-endian

format.

Control

tsv[7:0]

tsv[15:8]

Address

Memory

Description

0120h

0121h

0122h

016Ah

016Bh

016Ch

016Dh

0Eh

PHUGEEN, PPADN,

Destination Address,

016Eh

Start of the Next Packet

tsv[23:16]

tsv[31:24]

data[1]

data[2]

tsv[39:32]

tsv[47:40]

tsv[55:48]

0159h

0157h

0158h

0156h

data[m]

Data Packet

Status Vector

ETXST = 0120h

ETXND = 0156h

Type/Length and Data

PCRCEN and POVERRIDE

Written by the Hardware

Source Address,

Buffer Pointers

ENC28J60-C/ML 数据表(PDF) 42 Page - Microchip Technology

ENC28J60-C/ML 数据表(HTML) 42 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

数据表下载