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ENC28J60-C/ML 数据表(PDF) 63 Page - Microchip Technology

部件名 ENC28J60-C/ML
功能描述  Stand-Alone Ethernet Controller with SPI Interface
PDF  96 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

ENC28J60-C/ML 数据表(HTML) 63 Page - Microchip Technology

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© 2006 Microchip Technology Inc.
Preliminary
DS39662B-page 61
ENC28J60
11.5
PHY Subsystem Reset
The PHY module may be reset by writing a ‘1’ to the
PRST bit in the PHCON1 register (Register 11-1). All
the PHY register contents will revert to their Reset
defaults.
Unlike other Resets, the PHY cannot be removed from
Reset immediately after setting PRST. The PHY
requires a delay, after which the hardware automati-
cally clears the PRST bit. After a Reset is issued, the
host controller should poll PRST and wait for it to
become clear before using the PHY.
REGISTER 11-1:
PHCON1: PHY CONTROL REGISTER 1
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
U-0
R/W-0
PRST
PLOOPBK
—
—
PPWRSV
r
—
PDPXMD
bit 15
bit 8
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
r
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
PRST: PHY Software Reset bit
1
= PHY is processing a Software Reset (automatically resets to ‘0’ when done)
0
= Normal operation
bit 14
PLOOPBK: PHY Loopback bit
1
= All data transmitted will be returned to the MAC. The twisted-pair interface will be disabled.
0
= Normal operation
bit 13-12
Unimplemented: Read as ‘0’
bit 11
PPWRSV: PHY Power-Down bit
1
= PHY is shut down
0
= Normal operation
bit 10
Reserved: Maintain as ‘0’
bit 9
Unimplemented: Read as ‘0’
bit 8
PDPXMD: PHY Duplex Mode bit
1
= PHY operates in Full-Duplex mode
0
= PHY operates in Half-Duplex mode
bit 7
Reserved: Maintain as ‘0’
bit 6-0
Unimplemented: Read as ‘0’



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