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ENC28J60-C/ML 数据表(PDF) 69 Page - Microchip Technology

部件名 ENC28J60-C/ML
功能描述  Stand-Alone Ethernet Controller with SPI Interface
PDF  96 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

ENC28J60-C/ML 数据表(HTML) 69 Page - Microchip Technology

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© 2006 Microchip Technology Inc.
Preliminary
DS39662B-page 67
ENC28J60
REGISTER 12-4:
PHIE: PHY INTERRUPT ENABLE REGISTER
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
rr
rrrr
rr
bit 15
bit 8
R-0
R-0
R/W-0
R/W-0
R-0
R-0
R/W-0
R/W-0
rr
r
PLNKIE
r
r
PGEIE
r
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-6
Reserved: Write as ‘0’, ignore on read
bit 5
Reserved: Maintain as ‘0’
bit 4
PLNKIE: PHY Link Change Interrupt Enable bit
1
= PHY link change interrupt is enabled
0
= PHY link change interrupt is disabled
bit 3-2
Reserved: Write as ‘0’, ignore on read
bit 1
PGEIE: PHY Global Interrupt Enable bit
1
= PHY interrupts are enabled
0
= PHY interrupts are disabled
bit 0
Reserved: Maintain as ‘0’
REGISTER 12-5:
PHIR: PHY INTERRUPT REQUEST (FLAG) REGISTER
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
rr
rrrr
rr
bit 15
bit 8
R-x
R-x
R-0
R/SC-0
R-0
R/SC-0
R-x
R-0
r
r
r
PLNKIF
r
PGIF
r
r
bit 7
bit 0
Legend:
R = Readable bit
SC = Self-clearing bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-6
Reserved: Do not modify
bit 5
Reserved: Read as ‘0’
bit 4
PLNKIF: PHY Link Change Interrupt Flag bit
1
= PHY link status has changed since PHIR was last read; resets to ‘0’ when read
0
= PHY link status has not changed since PHIR was last read
bit 3
Reserved: Read as ‘0’
bit 2
PGIF: PHY Global Interrupt Flag bit
1
= One or more enabled PHY interrupts have occurred since PHIR was last read; resets to ‘0’ when read
0
= No PHY interrupts have occurred
bit 1
Reserved: Do not modify
bit 0
Reserved: Read as ‘0’



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