CS8420-CSZ datasheet(46/94 Pages) CIRRUS

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DS245F4

CS8420

10.18 User Data Buffer Control (13h)

User data pin (U) direction specifier

0 - The U pin is an input. The U data is latched in on both rising and falling edges of

OLRCK. This setting also chooses the U pin as the source for transmitted

U data (default).

1 - The U pin is an output. The received U data is clocked out on both rising and falling edges

of ILRCK. This setting also chooses the U data buffer as the source of transmitted

U data.

UBM[1:0]

Sets the operating mode of the AES3 U bit manager

00 - Transmit all zeros mode (default)

01 - Block mode

10 - Reserved

11 - IEC consumer mode B

DETUI

D to E U-data buffer transfer inhibit bit (valid in block mode only).

0 - Allow U-data D to E buffer transfers (default)

1 - Inhibit U-data D to E buffer transfers

EFTUI

E to F U-data buffer transfer inhibit bit (valid in block mode only).

0 - Allow U-data E to F buffer transfers (default)

1 - Inhibit U-data E to F buffer transfer

Q-Channel Subcode Bytes 0 to 9 (14h - 1Dh) (Read Only)

The following 10 registers contain the decoded Q-channel subcode data

Each byte is LSB first with respect to the 80 Q-subcode bits Q[79:0]. Thus bit 7 of address 14h is Q[0] while

bit 0 of address 14h is Q[7]. Similarly bit 0 of address 1Dh corresponds to Q[79].

76543210

UBM1

UBM0

DETUI

EFTUI

76543210

CONTROL

ADDRESS

TRACK

INDEX

MINUTE

SECOND

FRAME

ZERO

ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE

ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND

ABS FRAME

CS8420-CSZ 数据表(PDF) 46 Page - Cirrus Logic

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