CS8420-CSZ datasheet(37/94 Pages) CIRRUS

37 / 94 page

DS245F4

CS8420

10.5

Clock Source Control (04h)

This register configures the clock sources of various blocks. In conjunction with the Data Flow

Control register, various Receiver/Transmitter/Transceiver modes may be selected.

RUN

The RUN bit controls the internal clocks, allowing the CS8420 to be placed in a

“powered down”, low current consumption, state.

0 - Internal clocks are stopped. Internal state machines are reset. The fully static

control port is operational, allowing registers to be read or changed. Reading and

writing the U and C data buffers is not possible. Power consumption is low (default).

1 - Normal part operation. This bit must be written to the 1 state to allow the CS8420

to begin operation. All input clocks should be stable in frequency and phase when

RUN is set to 1.

CLK[1:0]

Output side master clock input (OMCK) frequency to output sample rate (Fso) ratio selector. If

these bits are changed during normal operation, then always stop the CS8420 first (RUN = 0),

then write the new value, then start the CS8420 (RUN = 1).

00 - OMCK frequency is 256*Fso(default)

01 - OMCK frequency is 384*Fso

10 - OMCK frequency is 512*Fso

11 - reserved

OUTC

Output Time Base

0 - OMCK input pin (modified by the selected divide ratio bits CLK1 & CLK0,

(default)

1 - Recovered Input Clock

INC

Input Time Base Clock Source

0 - Recovered Input Clock (default)

1 - OMCK input pin (modified by the selected divide ratio bits CLK1 & CLK0)

RXD[1:0]

Recovered Input Clock Source

00 - 256*Fsi, where Fsi is derived from the ILRCK pin (only possible when the

serial audio input port is in Slave mode, default)

01 - 256*Fsi, where Fsi is derived from the AES3 input frame rate

10 - Bypass the PLL and apply an external 256*Fsi clock via the RMCK pin. The AES3

receiver is held in synchronous reset. This setting is useful to prevent UNLOCK

interrupts when using an external RMCK and inputting data via the serial audio

input port.

11 - Reserved

RUN

CLK1

CLK0

OUTC

INC

RXD1

RXD0

CS8420-CSZ 数据表(PDF) 37 Page - Cirrus Logic

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