CS8420-CSZ datasheet(67/94 Pages) CIRRUS

67 / 94 page

DS245F4

CS8420

13.5

Hardware Mode 4 Description

(Transceive Data Flow, No SRC)

Hardware mode 4 data flow is shown in Figure 27. Audio data is input via the AES3 receiver, and routed to

the serial audio output port. Different audio data synchronous to RMCK may be input into the serial audio

input port, and output via the AES3 transmitter.

The channel status data, user data, and validity bit information are handled in two alternative modes: 4A

and 4B, determined by a start-up resistor on the COPY pin. In mode 4A, the received PRO, COPY, ORIG,

EMPH, and AUDIO channel status bits are output on pins. The transmitted channel status bits are copied

from the received channel status data, and the transmitted U and V bits are 0.

In mode 4B, only the COPY and ORIG pins are output, and reflect the received channel status data. The

transmitted channel status bits, user data, and validity bits are input serially via the PRO/C, EMPH/U, and

AUDIO/V pins. Figure 20 shows the timing requirements.

The APMS pin allows the serial audio input port to be set to master or slave.

If a validity, parity, bi-phase, or lock receiver error occurs, the current audio sample is passed unmodified

to the serial audio output port.

Start-up options are shown in Table 13, and allow choice of the serial audio output port as a master or slave,

whether TCBL is an input or an output, the audio serial ports formats, and the source of the transmitted C,

U, and V data.

The following pages contain the detailed pin descriptions for Hardware mode 4.

AES3

Encoder

&Tx

Serial

Audio

Output

AES3 Rx

Decoder

C&Ubit Data Buffer

RXP

RXN

OLRCK

OSCLK

SDOUT

TXP

TXN

RMCK

RERR

COPY ORIG EMPH/U AUDIO/V

TCBL

DFC0

DFC1

VD+

H/S

Power supply pins (VD+, VA+, DGND, AGND) & the reset pin (RST) and the PLL filter pin (FILT)

are omitted from this diagram. Please refer to the Typical Connection Diagram for hook-up details.

VD+

Serial

Audio

Input

ILRCK

ISCLK

SDIN

PRO/C

APMS

Figure 27. Hardware Mode 4 - Transceive Data Flow, Without SRC

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