CS8420-CSZ datasheet(40/94 Pages) CIRRUS

40 / 94 page

DS245F4

CS8420

10.8

Interrupt 1 Register Status (07h) (Read Only)

For all bits in this register, a “1” means the associated interrupt condition has occurred at least

once since the register was last read. A”0” means the associated interrupt condition has NOT

occurred since the last reading of the register. Reading the register resets all bits to 0, unless

the interrupt mode is set to level and the interrupt source is still true. Status bits that are masked

off in the associated mask register will always be “0” in this register. This register defaults to 00.

TSLIP

AES3 transmitter source data slip interrupt. In data flows with no SRC, and where OMCK, which

clocks the AES3 transmitter, is asynchronous to the data source, this bit will go high every time

a data sample is dropped or repeated. Also, when TCBL is an input, and when the SRC is not

in use, this bit will go high on receipt of a new TCBL signal.

OSLIP

Serial audio output port data slip interrupt. When the serial audio output port is in Slave mode,

and OLRCK is asynchronous to the port data source, this bit will go high every time a data sam-

ple is dropped or repeated. Also, when the SRC is used, and the SRC output goes to the output

serial port configured in Slave mode, this bit will indicate if the ratio of OMCK frequency to OL-

RCK frequency does not match what is set in the CLK1 and CLK0 bits.

SRE

Sample rate range exceeded indicator. Occurs if Fsi/Fso or Fso/Fsi exceeds 3.

OVRGL

Over-range indicator for left (A) channel SRC output. Occurs on internal over-range for left

channel data. Note that the CS8420 automatically clips over-ranges to plus or minus full scale.

OVRGR

Over-range indicator for right (B) channel SRC output. Occurs on internal over-range for right

channel data. Note that the CS8420 automatically clips over-ranges to plus or minus full scale

DETC

D to E C-buffer transfer interrupt. The source for this bit is true during the D to E buffer transfer

in the C bit buffer management process.

EFTC

E to F C-buffer transfer interrupt. The source for this bit is true during the E to F buffer transfer

in the C bit buffer management process.

RERR

A receiver error has occurred. The Receiver Error register may be read to determine the nature

of the error which caused the interrupt.

TSLIP

OSLIP

SRE

OVRGL

OVRGR

DETC

EFTC

RERR

CS8420-CSZ 数据表(PDF) 40 Page - Cirrus Logic

CS8420-CSZ 数据表(HTML) 40 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94

数据表下载