CS8420-CSZ datasheet(76/94 Pages) CIRRUS

76 / 94 page

DS245F4

CS8420

13.7.1

Pin Description - Hardware Mode 6

Overall Device Control:

DFC0, DFC1 - Data Flow Control Inputs

DFC0 and DFC1 inputs determine the major data flow options available in Hardware mode, according to Table 5.

S/AES - Serial Audio or AES3 Input Select

S/AES is connected to VD+ in Hardware mode 6, in order to select the serial audio input.

SFMT0, SFMT1 - Serial Audio Input Port Data Format Select Inputs

SFMT0 and SFMT1 select the serial audio input port format. See Table 15.

OMCK - Output Section Master Clock Input

Output section master clock input. The frequency must be 256x the output sample rate (Fso).

Audio Input Interface:

SDIN - Serial Audio Input Port

Data Input Audio data serial input pin.

ISCLK - Serial Audio Input Port Bit Clock

Input or Output Serial bit clock for audio data on the SDIN pin.

*Pins which remain the same function in all modes.

COPY/C

DFC0

EMPH

SFMT0

SFMT1

VA+

AGND

FILT

RST

APMS

TCBLD

ILRCK

ISCLK

SDIN

*24

*23

*22

ORIG

DFC1

TXP

TXN

H/S

VD+

DGND

OMCK

S/AES

AUDIO

CEN

TCBL

CS8420-CSZ 数据表(PDF) 76 Page - Cirrus Logic

CS8420-CSZ 数据表(HTML) 76 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94

数据表下载