CS8420-CSZ datasheet(32/94 Pages) CIRRUS

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DS245F4

CS8420

10. CONTROL PORT REGISTER BIT DEFINITIONS

10.1

Memory Address Pointer (MAP)

This register defaults to 01

INCR

Auto-Increment Address Control Bit

0 -

Auto-increment address off

1 -

Auto-increment address on

MAP6-MAP0

0 -

Reserved

1 -

Misc. Control 1

2 -

Misc. Control 2

3 -

Data Flow Control

4 -

Clock Source Control

5 -

Serial Audio Input Port Data Format

6 -

Serial Audio Output Port Data Format

7 -

Interrupt Register 1 Status

8 -

Interrupt Register 2 Status

9 -

Interrupt Register 1 Mask

10 -

Interrupt Register1 Mode (MSB)

11 -

Interrupt Register 1 Mode (LSB)

12 -

Interrupt Register 2 Mask

13 -

Interrupt Register 2 Mode (MSB)

14 -

Interrupt Register 2 Mode (LSB)

15 -

Receiver Channel Status Bits

16 -

Receiver Error Status

17 -

Receiver Error Mask

18 -

Channel Status Data Buffer Control

19 -

User Data Buffer Control

20 to 29 -

Q-channel Subcode Bytes 0 to 9

30 -

Sample Rate Ratio

31 -

Reserved

32 to 55 -

C-bit or U-bit Data Buffer

56 to 126 - Reserved

127 -

Chip ID and version register

Reserved registers must not be written to during normal operation. Some reserved registers are used for

test modes, which can completely alter the normal operation of the CS8420.

INCR

MAP6

MAP5

MAP4

MAP3

MAP2

MAP1

MAP0

CS8420-CSZ 数据表(PDF) 32 Page - Cirrus Logic

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