CS8420-CSZ datasheet(31/94 Pages) CIRRUS

31 / 94 page

DS245F4

CS8420

9.2

I²C Mode

In I²C mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL, with

the clock to data relationship as shown in Figure 23. There is no CS pin. Each individual CS8420 is given a

unique address. Pins AD[1:0] form the two least significant bits of the chip address and should be connected

to VD+ or DGND as desired. The EMPH pin is used to set the AD2 bit, by connecting a resistor from the

EMPH pin to VD+ or to DGND. The state of the pin is sensed while the CS8420 is being reset. The upper

four bits of the 7-bit address field are fixed at 0010b. To communicate with a CS8420, the chip address field,

which is the first byte sent to the CS8420, should match 0010b followed by the settings of the EMPH, AD1,

and AD0. The eighth bit of the address is the R/W bit. If the operation is a write, the next byte is the Memory

Address Pointer (MAP) which selects the register to be read or written. If the operation is a read, the con-

tents of the register pointed to by the MAP will be output. Setting the auto-increment bit in MAP allows suc-

cessive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. The ACK

bit is output from the CS8420 after each input byte is read and is input to the CS8420 from the microcon-

troller after each transmitted byte.

9.3

Interrupts

The CS8420 has a comprehensive interrupt capability. The INT output pin is intended to drive the interrupt

input pin on the host microcontroller. The INT pin may be set to be active-low, active-high, or active-low with

no active pull-up transistor. This last mode is used for active-low, wired-OR hook-ups, with multiple periph-

erals connected to the microcontroller interrupt input pin.

Many conditions can cause an interrupt, as listed in the interrupt status register descriptions. Each source

may be masked via mask registers. In addition, each source may be set to rising-edge, falling-edge, or level-

sensitive. Combined with the option of level-sensitive or edge-sensitive modes within the microcontroller,

many different set-ups are possible, depending on the needs of the equipment designer.

SDA

SCL

0010

AD2-0

R/W

Start

ACK

DATA7-0

ACK

DATA7-0

ACK

Stop

Note 2

Note 1

Note 3

Figure 23. Control Port Timing in

I²C Mode

AD2 is derived from a resistor attached to the EMPH pin

AD1, and AD0 are determined by the state of the corresponding pins.

If operation is a write, this byte contains the Memory Address Pointer, MAP.

If operation is a read, the last bit of the read should be NACK (high).

Notes:

CS8420-CSZ 数据表(PDF) 31 Page - Cirrus Logic

CS8420-CSZ 数据表(HTML) 31 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94

数据表下载