CSG14K_CSG8K datasheet(68/114 Pages) OSRAM

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CSG14K_CSG8K

Functional Description

Datasheet

• PUBLIC

DS000571

• v2-01 • 2023-Feb-10

113

│ 67

Figure 74:

Calculation Examples

Parameter

Example 1

Example 2

Image mode

IMG.1

IMG.4

fclk_in

12 MHz

Targeted data rate

1190 Mbit/s

1000 Mbit/s

PLL_WRAP_ADC_DIV

PLL_WRAP_MAIN_DIV

PLL_DIV

198

166

RG_CTRL

Effective data rate(1)

1188 Mbit/s

966 Mbit/s

(1)

The effective data rate is equal to the available bandwidth and does not take into account any overhead data.

As described in section 7.2.2, a PLL lock time of maximum 1 ms needs to be respected. The

lock status of a PLL can be checked by polling the read-only PLL_LOCK register.

The PLL_LOCK registers are only present in the two sequencers. The bottom-side sequencer

(with BLOCK_ID 0) holds the lock information of the bottom-side PLL. The top-side sequencer

(with BLOCK_ID 1) holds the lock information of the top-side PLL.

Figure 75:

PLL Lock Register

Bank

Addr

Read Value

PLL_LOCK

0: PLL out of lock

1: PLL locked

Set Data Interface

The sensor’s pixel data is transmitted over its sub-LVDS output channels. More information

on the output interface and low-level timing can be found in section 7.3. Figure 45 shows the

required register uploads to set the output format.

Figure 76:

Output Format Registers

Bank

Address

Value

OUTP_FORMAT

PLL_WRAP_MAIN_DIV

CLKGEN_BYTE_H

CLKGEN_BYTE_L

CSG14K_CSG8K 数据表(PDF) 68 Page - OSRAM GmbH

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