CSG14K_CSG8K datasheet(78/114 Pages) OSRAM

78 / 114 page

Document Feedback

CSG14K_CSG8K

Functional Description

Datasheet

• PUBLIC

DS000571

• v2-01 • 2023-Feb-10

113

│ 77

When a sequence is still active, a new rising edge on REQ_EXP will increment the remaining

number of frames by the value set in NROF_FRAMES. The total number of remaining frames

may not be higher than 255.

Shutter Lag

Figure 92:

Shutter Lag Register

Bank

Addr

Bits

Description

SHUTTER_LAG

[15:0]

See description below

PTR_EXP_0

112

[6:0]

Set differently depending on

whether the matching of the shutter

lag is enabled or disabled

Following the default configuration (see Figure 62); the shutter lag functionality is enabled,

resulting in a shutter lag delay equal to the equation below.

Equation 8:

��ℎ��_�� = ��,�� + 32 ∗ ��_��

The shutter lag matching can also be disabled:

Set the PTR_EXP_0 register to the image mode dependent value (see Figure 62)

Set the SHUTTER_LAG register to 0.

In this case, the shutter lag time becomes:

Equation 9:

��ℎ��_�� = 32 ∗ ��_��

Disabling shutter lag is not possible in the 10-bit short exposure more (IMG.2) and the 12-bit

short exposure mode (IMG.5).

7.5.2

Row Length

Figure 93:

Row Length Register

Bank

Addr

Bits

Description

ROW_LENGTH

18-19

[13:0]

See below

The row length trow defines the DVAL frequency during readout; it can be programmed in

number of CLK_PIX cycles with the ROW_LENGTH register.

CSG14K_CSG8K 数据表(PDF) 78 Page - OSRAM GmbH

CSG14K_CSG8K 数据表(HTML) 78 Page - OSRAM GmbH

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载