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CSG14K_CSG8K

Functional Description

Datasheet

• PUBLIC

DS000571

• v2-01 • 2023-Feb-10

113

│ 24

Figure 16:

Bias Voltages

Regulator Pin

Type

Bias Pin

Voltage [V]

Analog ref

VBGAP

1.24

Analog ref

BIAS_IDAC_RES

1.24

VPIX1_L_OUT

Pixel control

VPIX1_L_IN

-0.70

VDD33 (ext)

Pixel control

VPIX4_H_IN

3.30

VPIX1_H_OUT

Pixel control

VPIX1_H_IN

4.13

VPIX3_H_OUT

Pixel control

VPIX3_H_IN

3.83

VPIX2_H_OUT

Pixel control

VPIX2_H_IN

3.53

VPIX4_L_OUT

Pixel control

VPIX4_L_IN

0.73

VSSNEG

Pixel control

VPIX2_L_IN

-1.30

7.2.2

Startup Sequence

After the supply power-up sequence, the general sequence below (also shown in Figure 17)

must be followed to configure and start operating the sensor. Deviating from the order or

timing can lead to the sensor being in an unknown or unstable state.

The sensor hard reset pin, RST_N, must be asserted (‘0’) during the supply ramp-up to

initialize the sensor in the hard reset state. By releasing RST_N (‘1’), the sensor moves to soft

reset state. CLK_IN can be started during either the hard reset or during soft reset state

(there is no relation to the releasing of RST_N). During the soft reset state, the recommended

SPI uploads must be executed (see section 7.4.3). This includes ramping up VDD45 and

VSSNEG, and enabling the PLL, which locks after maximally 1 ms. After the PLL has locked,

the sensor can be moved from soft reset state to idle state through a short SPI upload.

In idle state, the sensor waits for an exposure request to begin grabbing, for example with the

REQ_EXP pin (depending on the configured sensor control mode).

As indicated in the figure, a non-overlap of 1 µs must be respected between each sensor

state change and the next action.

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