CSG14K_CSG8K datasheet(98/114 Pages) OSRAM

98 / 114 page

Document Feedback

CSG14K_CSG8K

Functional Description

Datasheet

• PUBLIC

DS000571

• v2-01 • 2023-Feb-10

113

│ 97

The status bits can be enabled on the CTRL channel or observed on one of the digital test

output pins.

Attention

Enabling the not-safe-to-request status bits on the CTRL channel might influence the control word in

idle state. It is therefore recommended to perform control channel training with EN_NSF set to ‘0’.

7.8.4

Digital Test Output

Figure 124:

Digital Test Output Register

Reg. Name

Bank

Addr

Bits

Description

DMUX1_SEL

50-51

[9:5]

Sets pin TDIG1 function

DMUX2_SEL

50-51

[14:10]

Sets pin TDIG2 function

A number of digital signals of the chip can be monitored in real-time during normal sensor

operation via the sensor output pins TDIG1 to TDIG4. This can be useful for testing and

debugging the system without having to rely on the sub-LVDS implementation of the control

channel, so a test pad or connection to the FPGA is recommended.

Selecting which signal to be monitored is done with DMUX1_SEL registers for TDIG1

(bottom) and TDIG3 (top) and with DMUX2_SEL registers for TDIG2 (bottom) and TDIG4

(top).

Figure 125:

TDIG Mapping

DMUX*_SEL

Description

PLL lock status

Global sampling phase(1)

Exposure status (group S)

Exposure status (group L)

EOBVAL

SVAL

FVAL

DVAL

NSRF (Not-Safe-to request frame status bit)

NSRE (Not-Safe-to request exposure status bit)

(1)

GLOB time seen on TDIG pin is only a fraction of the real GLOB time. GLOB program still extends after

falling edge of this signal.

CSG14K_CSG8K 数据表(PDF) 98 Page - OSRAM GmbH

CSG14K_CSG8K 数据表(HTML) 98 Page - OSRAM GmbH

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载