CSG14K_CSG8K datasheet(71/114 Pages) OSRAM

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CSG14K_CSG8K

Functional Description

Datasheet

• PUBLIC

DS000571

• v2-01 • 2023-Feb-10

113

│ 70

Figure 80:

Release Soft Reset Sequence

Bank

Address

Value

CMD_REGS

EN_CLK_MAIN

241

243

EN_ADC_RST_N

101

EN_CLK_ADC

100

Assert Soft Reset

To return the sensor to the soft reset state, the following register uploads need to be applied.

Figure 81:

Assert Soft Reset Sequence

Bank

Address

Value

CMD_REGS

EN_CLK_MAIN

240

EN_ADC_RST_N

101

EN_CLK_ADC

100

Asserting the soft reset does not affect the PLL. However, internal clock generation and

distribution are disabled when the soft reset is asserted. The soft reset has to be released

again before any frames can be grabbed.

Attention

Asserting the soft reset stops the output drivers. Any phase alignment done by the external system

is lost and should be redone when the soft reset is released.

Set ROI

Refer to section 7.5.3 for details on configuring the vertical ROI. Refer to section 7.5.4 for

details on configuring the horizontal ROI.

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