CSG14K_CSG8K datasheet(50/114 Pages) OSRAM

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CSG14K_CSG8K

Functional Description

Datasheet

• PUBLIC

DS000571

• v2-01 • 2023-Feb-10

113

│ 49

By using the three registers defined above, the sensor can in theory be controlled with just the

SPI interface plus 2 timing inputs (RST_N and CLK_IN) at the cost of a slightly reduced timing

accuracy (because the registers are loaded via the SPI interface).

The two HALT commands can be used to stop any active sensor operation and return the

sensor to the IDLE state, waiting for new requests. The difference between the two is:

●

CMD_HALT_BLOCK: When asserted, the active READOUT is finished before moving

to IDLE state.

●

CMD_HALT_NBLOCK: When asserted, all the operations are stopped immediately

and the sensor directly moves to IDLE state.

The HALT commands are a good way to get the sensor out of the Streaming control mode

without asserting any reset.

7.3

Sensor Readout Format

The sensor puts out image data in a format similar to the CMV sensor family. Sub-LVDS

channels are used for data transfer, with separate clock and control channels running in

parallel, to be used for data sampling and sync codes.

The CSG14K_CSG8K has sub-LVDS (low voltage differential signaling) outputs to transport

the image data to the surrounding system. Data is read out simultaneously from both sides

(top and bottom) of the pixel array. The sensor has the following channels on each side:

●

8 Data channels

●

1 OB data channel (optional)

●

1 Control channel

●

1 Clock channel

In total, the sensor has 22 sub-LVDS output pairs (2 pins for each sub-LVDS channel). This

means that a total of 44 pins of the CSG14K_CSG8K are used for the sub-LVDS outputs. See

the pin list for the exact pin numbers of the sub-LVDS outputs.

The data channels are used to transfer the pixel data from the sensor to the receiver in the

surrounding system.

The output clock channel transports a clock, synchronous to the data on the other sub-LVDS

channels. This clock should be used at the receiving end to sample the data. This clock is a

DDR clock, which means that the frequency will be half of the output data rate. When

1250 Mbit/s output data rate is used, the sub-LVDS output clock will be 625 MHz.

Information

The top and bottom output channels are not aligned. The user should use the top side

clock and control channels to evaluate the top data channels, and the bottom side clock

and control channels to evaluate the bottom data channels.

CSG14K_CSG8K 数据表(PDF) 50 Page - OSRAM GmbH

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